Mohammad Jundi
Newberry,FL
Summary
DC-DC Power Management designer. Experienced Analog Design Engineer with 10+ years in driving innovation in circuit design. Expert in LDO, Voltage Reference, Switching Regulators, analog TFM system.
Overview
1
1
Certificate
18
18
years of professional experience
Work History
SOC/Analog IC Engineer, Power Management
Intel Corporation
07.2006 - 11.2024
- Part of the Power Delivery IP: FIVR Power System team which designed a synchronous 140 MHz multi-phase buck regulators, featuring up to 80 MHz unity gain bandwidth. Designed several converter related auxiliary IPs, carried them through implementation, simulation, layout, and production
- Designed a VMC buck DC/DC converter 12V/1.2V with 10A output, Switching Frequency of 500kHz with Type III Compensator, using SIMPLIS.
- Designed a fixed-frequency current-mode-controlled boost converter delivering 15 V 1 A from a 8-V source.
- Designed a synchronous 20MHz VMC DC-DC buck converter 2.7V/1.2V with 600MA load, with 3-poles 2-zeros Compensator, using LTSPICE/SIMPLIS
- Designed, implemented and simulated Current-Mode digitally controlled PWM Buck converter 15/5V with slope compensation in LTSPICE.
- Designed Innovative High-Voltage Regulator (LDO) with Wide Dynamic-Range and High PSRR, designed Precise Adaptive Voltage-Reference (VR) with Process-Tracking and Temperature-Compensation.
- Designed global biasing generating ~40 current sources of 100uA thru current-routing. Collaborate with mask designer to construct layout collaterals
- Supported analog TFM system covered simulation methodology, parasitic estimation/extraction, Reliability flows, TSMC/Intel PDK collaterals.
Education
Master of Science - Computer Engineering w/Thesis
University Of Louisiana At Lafayette
Lafayette, LA05.2006
Bachelor of Science - Electrical Engineering
University of Jordan
Amman Jordan08.1999
Skills
- Analog Circuit Design/PMIC
- Simulation Software
- Power Electronics/Device Physics
- Technical Leadership
Certification
Santa Clara University PhD Electrical Engineering classes; 2014 GPA 3.87: Analog Integrated Circuits I & II, Adv RF Design, Adv Analog IC, RF Integrated Circuit Design, Transistor Models for IC Design, VLSI Design I, Mix Signals IC Design for Data Communication, Semiconductor Dev Theory I.
Timeline
SOC/Analog IC Engineer, Power Management
Intel Corporation
07.2006 - 11.2024
Master of Science - Computer Engineering w/Thesis
University Of Louisiana At Lafayette
Bachelor of Science - Electrical Engineering
University of Jordan
HONORS & AWARDS
- DDG Division Recognition Award; Intel TMG Excellence Award: Helped accelerating the tape-out of a 14nm test chip 7 weeks earlier than the previous generation, reducing the average physical design effort for SDP FUBs by 50%.
- Intel TMG LTD Department Recognition; Intel TMG CDS/CCT Department Recognition award: Awarded four times for outstanding performance.
- Full Scholarship in the Graduate School; BSc college scholarships and high school and for outstanding academic record.
HONORS & AWARDS
- DDG Division Recognition Award; Intel TMG Excellence Award: Helped accelerating the tape-out of a 14nm test chip 7 weeks earlier than the previous generation, reducing the average physical design effort for SDP FUBs by 50%.
- Intel TMG LTD Department Recognition; Intel TMG CDS/CCT Department Recognition award: Awarded four times for outstanding performance.
- Full Scholarship in the Graduate School; BSc college scholarships and high school and for outstanding academic record.