Aindrik Dutta
Digital Design Engineer
Seattle,WA
Summary
Dynamic and results-oriented RTL Design Engineer with over 10 years of hands-on experience in designing and implementing intricate digital circuits. Proven track record of delivering high-quality IPs for silicon-proven products, reflecting a strong commitment to excellence and innovation. Recognized for exceptional problem-solving skills and a collaborative approach that drives project success and enhances team performance. Dedicated to leveraging technical expertise to contribute to cutting-edge developments in digital design.
Overview
17
17
years of professional experience
Work History
Senior Staff Digital Design Engineer
Infineon Technologies
04.2025 - Current
Staff Digital Design Engineer
Infineon Technologies
08.2020 - 03.2025
- Work with AMS architects to define digital logic specifications and requirements of mixed signal ICs.
- Develop micro-architecture of digital control/data-path logic for Data Converter IP’s that meet PPA requirements, targeting ARM based Automotive MCUs.
- Develop test benches and unit tests to ensure a quality design before handing it to verification team.
- Work with verification team to develop test plans and debug issues in the digital design flow.
- Perform Lint, CDC and Power analysis to ensure design quality.
- Create timing constraints, UPF, run Synthesis and LEC for chip integration.
- Work with Physical Design team to close STA and implement required ECOs.
- Support validation test development, chip validation and characterization.
- Prepare and maintain documentation, including register TRMs, block and timing diagrams.
Senior Electrical Engineer
Microvision
01.2018 - 07.2020
- Design RTL for data acquisition and post processing of MEMS based laser projection and sensing device (short throw LIDAR).
- Responsibilities included microarchitecture, RTL development, simulation, IP integration, FPGA synthesis, timing closure and validation.
- Worked on implementing DSP algorithms and custom data processing logic targeting Xilinx Artix and Kintex7 FPGAs.
- Developed and maintained nightly FPGA build and validation framework.
- Automated back-end ASIC design task such a MMIO register map and top-level RTL Verilog code generation.
FPGA Engineer II
Meteorcomm LLC
06.2015 - 12.2017
- Firmware Engineer for a software defined radio product with Altera Cyclone III FPGA/TI C6747 DSP signal processing chain.
- Hands on experience in programming embedded systems and writing software with an RTOS (SMX)
- Development of new features both in the physical layer and application layer.
- Work closely with Hardware and Software team to research and implement higher symbol rate transmission capability in software defined radio firmware.
- Actively worked with the Test team to identify and fix existing and new bugs in the radio firmware.
- Participate in design meetings and story refinements following Agile methodology of development.
Teaching Assistant at Dept. of Elec & Comp Engg.
University of New Mexico
01.2013 - 12.2014
- TA and Lab Instructor a) Intermediate Programming and Engineering Problem Solving using C++ b) Circuit Analysis I c) Computer Logic Design using VHDL.
Research Assistant at Dept. of Elec & Comp Engg.
University of New Mexico
08.2011 - 12.2014
- Responsible for conducting research in Hardware Acceleration using FPGAs. Also involved in a project in Hardware Security using Physical Un-cloneable Functions.
Project Assistant at Microelectronics Div.
SINP, Kolkata, India
07.2008 - 02.2010
- Was responsible for conducting research in medical image processing. Worked on noise removal in ultrasound images and FPGA implementation of algorithms.
Education
M.S. - Computer Engineering
B.Tech. - Computer Science & Engineering
Skills
Proficient in RTL development, specializing in Verilog and SystemVerilog with excellent debugging skills
Strong foundation in digital design principles
Demonstrated expertise through successful implementation of digital and mixed-signal designs in various CMOS technology nodes
Chip integration experience leveraging mixed-signal DoT flows
PUBLICATIONS
Fareena Saqib, Aindrik Dutta, Jim Plusquellic, Philip Ortiz, Marios Pattichis, "Pipelined Decision Tree Classification Accelerator Implementation in FPGA", IEEE Transactions on Computers, Volume: 64, Issue: 1 Publication Year: 2015, Page(s): 280 – 285.
TOOLS
- Software/Tools: Questa Sim, Cadence Xcelium, Spyglass, Matlab, Simulink, Xilinx Vivado, MS Visio, Formality.
- Programming Languages: C, C++
- HDL: Verilog, System Verilog
- Interpreted Languages: Python, Tcl
- Version Control: Perforce, SVN, Git
- Operating Systems: Linux, Windows, MacOS
Timeline
Senior Staff Digital Design Engineer - Infineon Technologies
04.2025 - Current
Staff Digital Design Engineer - Infineon Technologies
08.2020 - 03.2025
Senior Electrical Engineer - Microvision
01.2018 - 07.2020
FPGA Engineer II - Meteorcomm LLC
06.2015 - 12.2017
Teaching Assistant at Dept. of Elec & Comp Engg. - University of New Mexico
01.2013 - 12.2014
Research Assistant at Dept. of Elec & Comp Engg. - University of New Mexico
08.2011 - 12.2014
Project Assistant at Microelectronics Div. - SINP, Kolkata, India
07.2008 - 02.2010
West Bengal University of Technology - B.Tech., Computer Science & Engineering
University of New Mexico - M.S., Computer Engineering