Alain Dargelas

• 1rst RS employee in engineering, grew the SW team to 57 employees in one year, recruited the VP of HW and Product Planning, created micro sites in 4 continents
• Architect/Principal developer of the whole Raptor SW suite (Quartus/Vivado equivalent) using open-source and close-source components
• Created the Device Modeling methodology with the HW team
• Created the SW and FPGA Validation methodology
• Contributed to the FPGA HW specification, especially Configuration, Security and SoC interfacing
• Drove the SW/HW QoR results to best-in-class in the industry
• Managed to tight budget FTE and consulting staff
• Engaged with 3rd party EDA vendors
• Groomed the next-generation leaders in my org in all sites

Active EDA open-source contributor. For the last 8 years, I contributed to several open-source EDA projects, notably:

https://github.com/os-fpga/Raptor(Architect - developer)

https://github.com/chipsalliance/Surelog(Architect – main developer)

• PSG FPGA Synthesis & Physical Synthesis 02/19 - 09/21: Manager of a 20-person team
• We create the RTL Synthesis (SystemVerilog/VHDL) and Physical Synthesis (Post-Route) software that Compiles/Optimize RTL designs into FPGA devices
• My team also develop Formal Verification flows around EDA vendor tools and develops internal Formal solutions
• PSG FPGA Device Modeling 01/18 - 02/19
• Acting Director of a 52-person organization, including 5 managers and a 10-person remote team in Penang responsible for multiple aspects of the Device Modeling, Configuration and Security features, Validation Board Design of our FPGAs
• Restructured the teams to fill all business needs, mentored the emerging management team
• Launched a retooling plan aiming at drastically reducing the turn-around time needed to add new Device Support to the Quartus Pro Software (1.4 years)
• Appointed as one of the Architects for the new Device Modeling methodology, an initiative spawning all Business Units
• Developed a SAT based methodology for Device Modeling (1-year coinciding with the Acting Director position)
• Managed the High-Speed Serial Interface Modeling team (11 eng.) that is responsible for the Quartus Pro Software Model of the FPGA SERDES (1.9 years)
• Managed the Core Fabric Device Modeling team (8 eng.) that is responsible for the Quartus II Software Model of the FPGA Device interconnect (1.5 years)

• Product line: VIPs
• Architect of the VIP template generator that allows templatized VIPs to be tuned to user’s needs (Eclipse RCP, System Verilog, Tcl)
• Co-implemented the Verilog DPI-based Verification Memory Model core in VCS (C++, SystemVerilog)
• Temporal logic, SAT, SVA self-training (2013)
• Product line: VCS/DVE: Architect for the Eclipse-based multi-debugger platform: SW/HW debug, Analog/Digital debug… (Java, RCP, Corba, QT, C++), assigned tasks to a team of 15 engs based in Shanghai, PRC
• US Patent 8,689,192 Natural Language Assertion Processor
• US Patent application 20110234600 Client/Server Waveform Viewer Using Bitmaps

• Joined this start-up in B-round funding
• Architected, coded along with my team (17 engs), and deployed the Analog Testbench language (Viper) and Testbench Builder GUI toolkit (TBB) which help analog designers to debug their designs prior to tape-out
• Duties included the China (Shanghai) operations setup, R&D hiring, management team training, hardware setup, multi-site networking setup, software purchase, roadmap and documentation creation, customer evaluation monitoring
• Presented at all board meetings the engineering team progresses

• Product planning and development for the timing exceptions verification tool TXV
• Wrote an ATPG (Automatic Test Pattern Generator) to solve the False Path and Multicycle path verification problems
• Managed a R&D team in India (Noida) to finalize the tool along with the clock domain checker product
• Monitored several evaluations at customer sites
• US Patent application 20060190754

• Product: LEDA
• Defined the Design Query Language Interface in C and Tcl that allows rapid development of topologically based user’s rules on full chip scale
• Developed a clock domain crossing rules including Gray code synchronization and automatic link with Formal Verification Model checker
• US Patent 7,263,675 Tuple propagator and its use in analysis of mixed clock domain designs
• Managed the LEDA Shanghai-based team to ensure customer rules development

• Products: Nova-ExploreRTL-Verilog/VHDL and Nova-Verilint which linted Verilog and VHDL language for synthesis, clocking, timing, semantic problems
• Trained and managed the Fremont and Shanghai-based team for the development of the Nova product
• Developed a RTL Virtual Prototyper
• Floor-planning, routing, timing estimation and interactive user placement on a 4 million gate equivalent RTL

• Product: Nova-ExploreRTL-Verilog
• Specification to implementation of RTL level design rule checking, including: DFT rules, clock domain analysis, case analysis, state machine analysis

• Ph.D Thesis subject: Automatic Test Pattern Generator for sequential circuits without reset
• ED&TC 97 (DATE) Paper: MOSAIC, Multiple Strategy Oriented Sequential ATPG for Integrated Circuits
• US Patent 5,938,785 Automatically determining test patterns for a netlist having multiple clocks and sequential circuits