Amsby Richardson Jr. (A.J.)

Supervised digital design team responsible for creating and implementing the digital components of voltage and current sensing design modules for automotive applications.

Role involved:

• Micro-architecture of digital features: autonomous ADC sequencers, data signal processing, alarm generation, etc.
• Mentored junior engineers, fostering skill development and knowledge sharing.
• Collaborated with cross-functional teams to troubleshoot process or system issues effectively (teams: software, analog, verification, chip-integration, test)

Digital design lead of autonomous ADC system IP for Intelligent Battery Sensor device PSOC™ 4 HVPA-144k , role involved:

• Engineered micro-architecture for digital features, optimizing partitioning for scalability and IP reusability.
• Successfully delivered IP usage specification and official register map, to ensure seamless software integration.
• Implementation of digital modules/features (e.g.):
• Multi Delta-Sigma Modulator ADC system w/ floating digital processing paths
• Auto-Gain controller: maximized result resolution for measurement ranges.
• SRAM based Finite Impulse Response (FIR) Filter w/ programmable coefficients
• Post Processor: averaging, glitch filters, threshold comparisons, etc.
• DFT planning for mixed-signal sub-system that achieved 99.8% test coverage
• Developed timing constraints, UPF file, and launched block level synthesis and ATPG
• Conducted LEC, CDC, and Multi-Voltage rule checking (MVRC) as part as IP sign-off.
• Optimized gate count: reduced 22% between test-chip IP and production IP

Digital Design owner of 4 IPs for Traveo II device family

• SPI external memory interface IP (SDR, DDR): constraint fixes and timing closure
• Audio DAC IP: design fixes and Design for Test (DfT) closure.
• Timer, Counter, PWM IP: Added design enhancement and took over design support
• Programmable Analog Sub-System IP ( primary project ), which involved:
• Engineered analog integration and parametrization for scalable IP reuse
• Implementation of digital modules/features (e.g.):
• Multi-SAR ADC System w/ programmable channel configurations
• HW/FW triggered start of sampling arbitration, scheduling, and pre-emption
• Averaging, threshold comparisons, and glitch filtering
• AHB Interface, Interrupts, HW triggers
• Provided timing constraints & UPF file; Ran IP ATPG, LEC, Lint, CDC, and MVRC

Co-designer of PSoC4 and PSoC6 programmable analog sub-systems IPs

• Highly programmable analog IP: analog routing, continuous time block, SAR ADC, programmable reference buffer, and DAC
• Created behavioral models for analog blocks to support digital verification and ATPG

Team lead for Universal Digital Block (UDB) IP for PCoC4 devices

• The UDB IP acted as a mini-FPGA and allowed customers to include programmable logic in a SoC device

Served as design representative for problem solving PSoC3 customers issues

• Converted customer application FW into simulations to determine root cause

Designer for Test Controller IP for PSoC5 LP device (ARM CPU).

• IP used to program, test, and debug the device via SWD, JTAG, and parallel mode.

Designer for 3 IPs for PSoC3 device (8051 CPU)

• Test Controller IP : Device interface for programming, testing, and debug. Interfaced with key IPs on the device such as the: boot logic, reset system, CPU, and the IOs. Communicated off-chip via JTAG and Serial Wire Debug (SWD)
• Debug On-Chip IP: standard debug functionality: halt, step, break, trace
• Serial Wire Viewer IP: 3rd Party IP from ARM, that provides a single wire output for instruction trace w/o entering a debug mode. I implemented the RTL wrapper and owned the device integration.

Automated the testing of firmware components that were delivered with the PSoC1 software suite with Perl scripting. These software components enhanced and simplified the customer application programming experience.