ANAND REDDY
San Jose,CA
Summary
High performing strategic leader with 20+ years of experience managing large scale semiconductor R&D teams focused on SOC and IP development. Proven track record of delivering industry leading CPUs, IPs and SOC products in the Client, Networking and Datacenter segments. Broad experience leading large engineering teams across sites worldwide through the product life cycle – definition to PRQ.
Overview
26
26
years of professional experience
Work History
Senior Director of IP Development
INTEL CORPORATION
01.2020 - Current
- Lead a team of 150+ engineers across multiple geographical sites (US, Malaysia, India) that design and deliver System IP (Power Management, Debug, Infrastructure, Manageability), Memory Controller IP, CXL and Accelerator IP for the Intel Client, Server, Graphics and Networking roadmap
- Manage a $10M+ annual budget to deliver 26 IPs while optimizing development and product cost
- Drove simplification of PM IP while converging on industry standards (P/Q channel) that led to a 2.5X reduction in silicon bug escapes and improved integration times at SOC
- Converged Debug and Infrastructure IP portfolio across client and server with flat headcount that saved $2M in costs, promoted reuse, improved quality and cut development time by 1 year
- Drove development of best-in-class memory controller IP that supports HBM, DDR and LPDDR technologies that are enabling custom products for cloud customers driving incremental business opportunities and millions of dollars of high margin revenue
- Drove the development of the CXL root port and device IP that significantly enhanced product performance especially for memory intensive applications, while also improving system efficiency and flexibility
- Drove development of custom accelerators for specific data workloads: streaming, in memory analytics
- Developed extensive risk reduction strategies (Test chips, HW-SW prototyping) for high quality first silicon bring up
- Responsible for executive monthly program level communication and stakeholder management of partner organizations across Intel (SOC teams, Firmware, Architecture, Tools, Business groups)
- Drove adoption of innovative, cost-effective industry leading solutions (formal, IP emulation, FPGA) that improve quality and achieve generational power/performance improvements
- Grow engineering leads, managers, Principal engineers, and Senior Principal engineers to build a high-performance team that can adapt to changing business needs and execute with urgency.
Senior Leader of Pre-silicon Power Management
INTEL CORPORATION
01.2012 - 01.2019
- Led a team of 25+ engineers responsible for power management design and verification on 5 Xeon generations of server processors – responsible for technical direction setting, planning and execution of all pre-silicon power management design/validation activities
- Pioneered hardware and firmware-based power management techniques that greatly improved time to market of server processors and improved performance per watt metric by 50%
- Drove 2X reduction in idle power that enabled server products to meet European Union and energy star regulatory requirements
- Owned pre-silicon verification of power management firmware (power and thermal algorithms) using cluster test environment, Full-chip simulation and emulation for 5 Xeon generations
- Shifted left 95% of firmware bug finding to pre-silicon through better modeling, co-validation with hardware and accelerating firmware development timeline
- Supported post-silicon teams on sighting resolution and meeting PnP targets for multiple Xeon generations (SKX, ICX, SPR, EMR, GNR).
SOC Validation Lead
INTEL CORPORATION
01.2006 - 01.2011
- Led pre-silicon full-chip validation using simulation and emulation of several server processors (Tulsa, Beckton, Ivy town)
- Supported post-silicon debug with sighting resolution
- Focus was on X-86 based feature architecture validation (MCA, Patching, Probe mode) and legacy validation (Interrupts, paging) through directed and random instruction-based testing techniques
- Pioneered development of random instruction-based testing environment that enabled quick isolation and resolution of processor bugs; 50 bugs were resolved using this environment in 2 months.
Individual Contributor Roles
INTEL CORPORATION
01.1999 - 01.2005
- Designed cache memory unit of 64-bit Intel CPU
- Owned functional pattern generation and validation for production stepping of a server processor (Madison) on the post-silicon tester team; The patterns increased functional coverage and improved the DPM (defects per million) of the product by 15%
- Debugged and developed test content for 20 functional and 15 speed path issues; speed related design fixes improved the processor frequency by 350 MHz’s.
Education
Master of Science in Computer Engineering -
UNIVERSITY OF WISCONSIN
Madison, WI12.1998
Bachelor of Science in Computer Science & Engineering -
UNIVERSITY OF MADRAS
Chennai, India04.1996
Skills
- Technical Expertise
- Strategic Thinking
- Culture Transformation
- Cross-functional Leadership
- Talent Management
Timeline
Senior Director of IP Development
INTEL CORPORATION
01.2020 - Current
Senior Leader of Pre-silicon Power Management
INTEL CORPORATION
01.2012 - 01.2019
SOC Validation Lead
INTEL CORPORATION
01.2006 - 01.2011
Individual Contributor Roles
INTEL CORPORATION
01.1999 - 01.2005
Master of Science in Computer Engineering -
UNIVERSITY OF WISCONSIN
Bachelor of Science in Computer Science & Engineering -
UNIVERSITY OF MADRAS
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