Anand Sudhini

Product Owner:

• Leading all T254 Pre-Si product development through active collaboration internally & with the external partner, writing collaboration documents, defining & aligning on product milestones & ownership.
• Leading the development of ATE HW including CP & FT load board designs by overseeing schematic creation, pinout determination, power delivery planning, and review of SI/PI simulations.
• Defining ATE test plans for NPI & MP, CHTOL/SHTOL test plan, Test sequence development for shared IPs, HSIO screening methodology & define merge flow methodology for ATE & CHTOL.
• Define ATE Fusing/binning strategy & Data sharing POR for the final product.
• Recommend solutions, built proposals, prepared supporting information and delivered F2F presentations to define POR for all test related activities

Sr. Product Engineer:

• Responsible for managing NPI from product definition and characterization, through specification validation, to product launch and ramp to MP.
• As CP/FT lead, I effectively oversaw the test program development for CP/FT, consistently enhancing quality and test coverage while minimizing Test Times & overall D0.
• Led critical Si debug to root cause yield issues affecting multiple products & drove CIPs incl. SYNC macro issue(CIP:2857429), Jtag_Extest (CIP:2773410)
• Developed test plans for introducing new test features while also leading the creation of new test methods and updating existing ones.
• As a qual lead, set aging margins with SSG, drove qual fail debug incl. EFA/PFA analysis & foundry teams to release new BKMs. Led program development & debug for CHTOL/PKG quals.
• Collaborated with cross-functional teams to address quality, reliability, and production issues while engaging with multiple engineering groups—Design, Layout, Foundry, SSG, and FA—to guide towards practical solutions

• Led all HTOL Board design activities including Schematic Capture, Layout Check/Review for all C-HTOL boards across Nvidia products using design tools ALLEGRO and AUTOCAD.
• Led all C-HTOL Board/Pattern Bring-Up (Logic, Mbist, CLKPLL) of all Nvidia products (GPUs and Tegras)
• Partnered with the HTOL socket vendor to create high-power HTOL sockets, which entailed designing, analyzing simulation outcomes, and ultimately choosing the optimal socket
• Automated board design file verification process & HTOL analysis with Python.
• Strong understanding of reliability failure modes & aging mechanisms including TDDB, BTI, HCI, EM.

• Managed the reliability ENG team of 2 engineers & 2 technicians, overseeing the design and assembly of Burn-In boards for MCC, INCAL, and AEHR test systems, ensuring compliance with customer netlist and specifications..
• Led HTOL bring-up, validation, and debugging processes using oscilloscopes, logic analyzers, spectrum analyzers.
• Responsible for Schematic Capture, Layout Checking and Reviewing using design tools including ALLEGRO and AUTOCAD.
• Responsible for Developing Test Plans to perform Functional and Reliability Testing on IC’s using C/C++ on Linux Test Platforms