Summary
Overview
Work History
Education
Skills
Awards and Achievements
Select Patents
Select Publications
Websites
References
Timeline
Generic

Angeline Smith

Cornelius,USA

Summary

Senior Process Engineer with 8+ years of experience in semiconductor R&D at Intel, focusing on thin film ALD/PVD module development. Achievements include significant advancements in metal gate and contact processes, leading to improved yield and device performance. Strong background in applying empowering leadership to build highly effective teams, and contribute to innovative business development.

Overview

14
14
years of professional experience

Work History

Senior Process Engineer/Manager

Intel Corporation
06.2016 - Current
  • Led the implementation of a novel work function metal stack for the 18A technology node, resulting in a +10% NMOS drive, a +4% FROS gain, and a 30 mV VTP reduction—delivered and implemented in under one quarter.
  • Developed an advanced metal gate process for the 7nm technology node, achieving a 4% WIW uniformity improvement, and eliminated chamber drift, accelerating qualification by one quarter to meet HVM demands.
  • Drove eNVM magnetic tunnel junction stack development, enabling greater than 10¹² cycle endurance and 690 RISO yield.
  • Drove PVD development for Via applications to enable new material implementation, and first-of-its-kind tool installation and qualification for process support.
  • Spearheaded equipment vendor evaluations, leading to the selection and optimization of best-in-class tools for improved performance, throughput, and cost reduction.
  • Managed a cross-functional team for over 2 years, set module goals, and met critical milestones while fostering an environment where engineers with diverse opinions and skill sets could develop and thrive.
  • Served as 'Team-of-3' Lead for the University of Minnesota, establishing partnerships for funding and recruiting opportunities.
  • Served as LTD metals area hiring manager to bring diverse, highly skilled talent to Intel.
  • Developed training curriculum and certification requirements for engineers and technicians.

Graduate Research Assistant

University of Minnesota
01.2011 - 05.2016
  • Designed, fabricated, and characterized nano-scale magnetic devices for memory and logic applications, including All-Spin logic, MQCA, and spin Hall devices.

Components Research Intern

Intel Corporation
05.2015 - 07.2015
  • Designed layout, fabricated, and performed device testing for All-Spin logic devices for magnetic based logic applications.

Education

Ph.D. - Electrical Engineering

University of Minnesota
Minneapolis, MN
01.2016

Master of Science - Electrical Engineering

University of Minnesota
Minneapolis, MN
01.2014

Bachelor of Science - Physics

University of Wisconsin – La Crosse
La Crosse, WI
01.2011

Skills

  • Semiconductor fabrication
  • Process and equipment development
  • Materials characterization
  • Team management
  • Resource planning
  • Thin film deposition (ALD, PVD)
  • SQL and data analysis
  • Statistical process control (SPC)
  • Data visualization with Power BI

Awards and Achievements

  • 23+ US patents granted
  • 2 Intel LTD Divisional Awards + multiple Area Recognition Awards
  • Co-author of book chapters on magnetic devices in two books
  • Author of 9+ peer reviewed journal publications

Select Patents

  • US11411173B2, Perpendicular spin transfer torque devices with improved retention and thermal stability
  • US11476412B2, Perpendicular exchange bias with antiferromagnet for spin orbit coupling based memory
  • US11616192B2, Magnetic memory devices with a transition metal dopant at an interface of free magnetic layers and methods of fabrication
  • US11770979B2, Conductive alloy layer in magnetic memory devices and methods of fabrication

Select Publications

  • MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology, O. Golonzka et al. [co-author], 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2018, 18.1.1-18.1.4, 10.1109/IEDM.2018.8614620
  • 2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications, J. G. Alzate et al. [co-author], 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, 2.4.1-2.4.4, 10.1109/IEDM19573.2019.8993474

References

References available upon request.

Timeline

Senior Process Engineer/Manager

Intel Corporation
06.2016 - Current

Components Research Intern

Intel Corporation
05.2015 - 07.2015

Graduate Research Assistant

University of Minnesota
01.2011 - 05.2016

Ph.D. - Electrical Engineering

University of Minnesota

Master of Science - Electrical Engineering

University of Minnesota

Bachelor of Science - Physics

University of Wisconsin – La Crosse
Angeline Smith