Anirudha Behera

Hierarchical Schematic and Layout Design of 4-bit Carry Look-ahead Adder.

• Designed a 4-bit CLA adder schematic, Symbol, Testing Circuit, and Layout using Virtuoso.
• Performed Physical Verifications (LVS, DRC) and Parasitic Extraction using Calibre. Then Formal verification is performed using Formality and measured Power, Delay, and temperature using HSPICE.

Standard Cell-Based RTL to GDSII Design for 8-bit Accumulator

• Developed RTL code and TestBench, synthesized using DC. Optimized Placement and Route with Encounter by adding buffers for area, power, timing then Completed Formal Verification, generated GDSII.

Standard Cell-Based 32-bit Pipelined CPU Design with Modified New ALU Architecture (RTL to GDSII)

• Implemented 5 CPU models with ASIC flow for slack time optimization.
• Executed Synthesis, PNR, and opt then recorded optimized slack time, power, area. Obtained GDSII Layout.
• Utilized CSeA, CLA, CRA and CSA adders and comparator-CLA mix designs and compared their performance.
• I found CSeA has the highest and CRA has lowest performance speed.

CAD Tool Design for Static Timing Analysis by using TCL/Tk and C Programming

• Designed C code to calculate the required time, arrival time, and slack time from the given input vectors and optimized the code to save the output file separately.
• Designed a Static Timing Analysis CAD tool GUI using TCL/Tk, which can take set of inputs from the user and optimize the given input vector using implemented C code and display the output results on the GUI interface.

Multimedia Mobile Processor Configuration for Ultra-low Power Design in Modern VLSI

• System-Level: Coded Graph-based slack analysis in C. Optimized with Loop unrolling and catch technique. WATCH and CACTI tools were used. Achieved 85.68% power reduction.
• RTL-Level: Applied ACG, CCG, OCCG, LECG, ECG, hybrid techniques on MMP. Achieved max 109.75% power reduction. Used Formality, Model Sim, Power Compiler (DC) tools.