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Overview
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Education
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Anish Mandal

Pleasanton,CA

Summary

Accomplished Sr Computer Scientist at Adobe Inc, specializing in C++ and performance tuning. Proven track record in enhancing PDF rendering engines, achieving significant performance improvements. Adept at leading projects and collaborating with teams, demonstrating strong problem-solving skills and technical expertise in parallel programming, Verilog simulation, parallel simulation and compiler technology.

Overview

23
23
years of professional experience
1
1
Certification

Work History

Sr Computer Scientist

Adobe Inc
07.2021 - Current
  • Role : Individual Contributor
  • Project: Integration of core PDF library layer with Edge browser (July 12, 2021, until now).
  • Working as an individual contributor in the project to integrate pdf core library to Edge web browser.
  • Interesting projects include :
  • Enhancement and Productization of parallel rendering engine of the core pdf library
  • Enhancement of free-text annotations.
  • Implementation of Digital Signature technology as specified in pdf standard.
  • Responsible for rendering performance improvement for the pdf library
  • Analyze thousands of pdf corpus for potential performance bottleneck at various areas of rendering
  • Coming up with infrastructure to analyze, categorize and track progress
  • Deep dive into specific issues and assign them to responsible persons.
  • Worked on many issues myself to improve performance and meet project goal.

Sr Staff R&D

Synopsys Inc
07.2007 - 07.2021
  • Role : R&D owner of distributed compile technology
  • Project: Enhance/maintain and deploy distributed compilation technology in customer designs ( Jan 2021 to July 2021 )
  • Working with AEs to deploy this flow in various customer designs to help them with better compilation TAT.
  • Debug issues onsite, find out fix, co-ordinate with other R&D to get help when needed.
  • Work on performance concerns and helped on tuning if needed.
  • Role : Technical lead/owner of FGP technology
  • Project: Support for Fine-grained parallelism during run-time for the new simulator technology for DUT ( Jan 2020 until Jun 2021 )
  • Design and development of FGP implementation for simulation in the new simulator technology.
  • Designed several optimizations on top of the basic FGP technology resulting in up to 8-10X performance gain with 16 cores.
  • Worked on bringing up several designs and fine tuning their performance.
  • Worked with Application Engineers as well as other team members to help in specific areas whenever needed.
  • Guided other engineers in the team to support other technologies like debug, clock-tree optimization etc to support in FGP infra-structure.
  • Role : Individual Contributor responsible for design and implementation
  • Project: New code generator-cum-simulator for DUT ( Jan 2019 until Jan 2021. This is the base project for the FGP project described above )
  • New code-generator to generate compact code and aimed at reducing run-time and run-memory by keeping memory layout compact.
  • Responsible for developing the whole infra-structure from the scratch along with system architect.
  • Developed/Enhanced basic building blocks like simulation kernel, evaluation/propagation model from the very beginning of the project.
  • Some of the most important projects include :
  • Support of statement-gates : Completely implemented efficient statement-gate infra-structure and initial support.
  • Clock ungating : designed and implemented the basic infra-structure and initial support.
  • Levelization : Worked on improving and maintaining levelization algorithm.
  • Support for RTL flops.
  • Various grouping optimizations : Designed and implemented various optimizations aimed at reducing levels.
  • Parallel simulation : architected many important parts of parallel simulation support for this new code generator.
  • Overall owner of the parallel simulation part.
  • Responsible for performance tuning and trials of various designs.
  • Helping team : Having implemented many parts of this simulator, one of the roles was to help all other team members wherever my expertise was required.
  • Project : simulation-based waveform generator for emulation ( Jan 2017 to dec 2018 )
  • A simulation-based waveform generator is used to generate waveforms for emulation tool.
  • This technology is used so that emulation speed is not compromised while dumping waveform.
  • One of the early developers responsible for developing the core simulation engine of this technology while the boundary of emulation/simulation was handled by other engineers.
  • Support of congruency: In order for simulation behavior to match emulation, congruency support is the backbone of the waveform simulation.
  • Implemented the congruency support.
  • Project: GPU-based simulation/Fine-grained parallelism ( Jan 2015 to Dec 2016 ) : Developing parallel engine for simulation using many-core processing units of GPU.
  • Aim of the project is to speed-up simulation by generating CUDA code which can be used to exploit all cores of GPU.
  • Some significant work includes :
  • Worked as an individual contributor.
  • Responsible for designing and implementing different features and optimizations for building the GPU-based simulation engine.
  • Some Interesting projects include :
  • Support for System Verilog Assertion ( SVA) in GPU : SVAs are non-synthesizable, which is lowered to synthesizable constructs using some existing infra-structure.
  • My role was to use that infra-structure and define simulation model for these SVA constructs.
  • Designed and implemented scanopt optimization for simulation.
  • GPU-based simulator was implemented as co-simulator with new simulation engine working with original VCS simulator.
  • They communicated over an interface.
  • Worked on various enhancements in this layer.
  • Decompiler support for SV packages and other SV construct : We dump the design in text file for synthesis.
  • It is a non-trivial job since many transformations happen before this.
  • Optimizations to merge several logic gates into one logic-gate : Reduces number of levels of the design.
  • Project: System Verilog ( from Jun 2014 till dec 2015 ) – System Verilog team in VCS takes care of the support of SV features – compilation and simulation of all SV constructs.
  • Some important projects I was involved in :
  • Increasing capacity of number of classes per module
  • Support for tagged union
  • Performance improvement of always @
  • / always_comb blocks in presence of for-loop in the always body.
  • Support for net-type in context of virtual interface
  • Worked in quality improvement of dynamic events involving class reference, structure reference etc.
  • Supporting multi-driver detection in vcselab infra-structure for interface class references.
  • Manager-II R&D
  • Role : overall owner and architect of code coverage component
  • Project: VCS code coverage ( Jan 2010 until Jun 2014 ) – Managed.
  • Project: VCS code coverage ( Jul 2007 until Jan 2010 ) – Worked as individual contributor.
  • Code coverage component of VCS, hardware-language compilation-cum-simulation tool, used by various design companies.
  • Code coverage component is responsible to estimate line, condition, branch, toggle coverages.
  • All these different metrics measure different characteristics of the verification process and help estimate the strength of verification.
  • Some important projects I was involved in :
  • Support for dumping intermediate coverage data during simulation.
  • Flattened condition coverage : I came up with a new idea to solve this problem and designed and developed the piece of software myself.
  • Observability-based condition coverage : New idea of condition coverage.
  • Came up with this idea, designed the architecture and implemented.
  • This became a new metric of coverage in going forward.
  • New Database project : Porting the whole code coverage to new database format which is based on xml with c++ APIs.
  • Managed this project and led to its success.
  • The project team involved more than 10 engineers and the project went on for almost a year.
  • Delivered more than 10X performance in post-processing.
  • Partition compiler project : Partition compile for VCS was aimed at improving incremental compile TAT.
  • Responsible for architecting code coverage solution, managing the project and delivering on time.
  • I also have an additional responsibility of developing part of the project.
  • Release-based projects : Participated in planning, resource allocation, execution and delivery for coverage component for multiple releases.
  • People manager : Managed a team of 5-7 engineers including responsibility of their appraisal, compensation, promotion etc.

Lead Engineer

Interra Systems India Pvt. Ltd.
03.2004 - 07.2007
  • Since August 2006
  • Project: Cheetah and MVV – A verilog analyzer and a mixed mode elaborator.
  • My responsibilities include
  • Dump compatibility between 32-bit and 64-bit machines.
  • Support for backward dump compatibility, enabling user to use older dump with newer version of the product.
  • Full syntax and semantic support for operator overloading according to SystemVerilog LRM.
  • Support for ordering of source files according to the dependency between modules and packages.
  • Maintenance of elaboration flow of verilog and mixed designs through verilog configurations.
  • Implementation of new master-binding support for mixed mode designs in accordance with ModelSim simulator.
  • Jan 2006 to July 2006
  • Project: Formal Verification of DFT IPs (FPA) in Texas Instruments, Bangalore.
  • My responsibilities include
  • Performing formal verification of Test-Mode-Controller.
  • Performed formal verification for Test-Pin-Muxing and boundary scan cells associated with each system pin.
  • Verification of MDP functionality.
  • Developing framework to formally verify inter-connectivity between different sub-modules at the SoC level.
  • Partly involved in verification of PSC and PLL.
  • Perfomed verification of custom logic module of dBIST IP.
  • July 2005 to Oct 2005
  • Project: Formal Verification of Floating Point Accelarator (FPA) in Texas Instruments, Bangalore.
  • March 2004 to June 2005 & Nov 2005 to Dec 2005
  • Project: Jaguar – A vhdl analyzer.
  • My responsibilities include
  • Fixing bugs at different areas, reported by customers.
  • Support for evaluation of vhdl operators using C functions.
  • Maintenance of elaboration and evaluation flow of Jaguar.
  • Given support for evaluation of access types and file I/O operations defined by VHDL.
  • Achievements: Won Key Contributor Award for the year 2004-05 (Contribution towards Jaguar Project) and year 2005-06 (Contribution towards Formal Verification project.)

Software Engineer

Alumnus Software Limited
03.2003 - 03.2004
  • Project: Development of Network Verification Tool for MMS.

Cognizant Technology Solutions, India , Limited
Kolkata
08.2002 - 02.2003
  • Project: Software Quality Assurance Group, Tools.

Education

Bachelor of Engineering - Computer Science and Technology

Bengal Engineering and Science University
01.2002

Higher Secondary Examination - Science

B T Road Govt. Spond. High School
Kolkata
01.1998

Secondary Examination -

Baranagar Ramakrishna Mission High School
Baranagar
01.1996

Skills

  • C and C
  • CUDA programming
  • Python
  • Compiler technology
  • Performance tuning
  • Verilog
  • Verilog Simulation
  • Hardware Design
  • Fine-grained-parallelism
  • Parallel Programming
  • Purify
  • Valgrind
  • Workshop Debugger
  • Data Display Debugger
  • Xcode
  • Git
  • Perforce

Certification

  • Linear Algebra for Machine Learning and Data Science, https://www.coursera.org/account/accomplishments/records/RABGT8APB8A8
  • Calculus for Machine Learning and Data Science, https://www.coursera.org/account/accomplishments/records/A37AHC4A52G7
  • Neural Networks and Deep Learning, https://www.coursera.org/account/accomplishments/records/PECWYVJZELDJ

<Enter your own>

Title: Experienced Software Developer

Timeline

Sr Computer Scientist

Adobe Inc
07.2021 - Current

Sr Staff R&D

Synopsys Inc
07.2007 - 07.2021

Lead Engineer

Interra Systems India Pvt. Ltd.
03.2004 - 07.2007

Software Engineer

Alumnus Software Limited
03.2003 - 03.2004

Cognizant Technology Solutions, India , Limited
08.2002 - 02.2003

Bachelor of Engineering - Computer Science and Technology

Bengal Engineering and Science University

Higher Secondary Examination - Science

B T Road Govt. Spond. High School

Secondary Examination -

Baranagar Ramakrishna Mission High School

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Anish Mandal