ANKITA AGARWAL
Summary
Quality-driven Technical Lead well-versed in Micro-architecture, and low-power design for graphics products. Successful at building robust solutions for changing business needs. A driven professional enthusiastic about meeting market challenges with scalable technologies.
Overview
19
19
years of professional experience
Work History
Technical Lead/Manager
Intel Corporation
09.2022 - Current
- Specification Definition for multiple features in texture blocks, low power features, and performance debug events to create performance profiles on pri-silicon, emulation, and post-silicon
- Supervised a team of developers to successfully deliver high-quality RTL on time and within the power, performance, and area constraints
- Conducted thorough design reviews to identify potential issues and propose effective solutions early in the development process
- Presented technical information clearly and concisely to senior management, facilitating better decision-making.
- Mentored junior developers through regular 1-on-1 meetings, providing guidance on best practices, coding standards, and career growth opportunities
Staff Design Engineer
Intel Corporation
09.2018 - 09.2022
- Designed Sampler decompression block, address conversion from L1 to L2 cache
- Developed Specification for architecture level, unit level, and module level clock gating for Texture Sampler blocks to reduce Static Power
- Collaborated on defining performance debug components for bottleneck analysis, latency measurement, and utilization across all graphics clusters.
- Resolved complex Timing and Routing challenges through creative problem-solving and collaboration with interdisciplinary teams to attain a 20% frequency push.
Sr. Graphics Hardware Design Engineer
Intel Corporation
04.2013 - 09.2018
- Designed and executed Low-power Arbitration and Cache controller blocks for Level 2 graphics cache with a good understanding of MESI states, LRU algorithms, data storage, coherency protocol, and arbitration
- Collaborated with post-silicon validation teams to resolve silicon-level sightings on L2 cache
- Reduced development time for projects by streamlining the hardware design process and collaborating effectively with cross-functional teams
- Mentored junior engineers, fostering a culture of continuous learning and professional growth
Sr. Design Engineer
Intel Corporation
04.2009 - 04.2013
- Owned Architecture specification definition and RTL coding for several units like Routing channels, L2 Ingress Arbiter, L2 Egress Arbiter, State Arbiter, and Flush controller
- Reduced power by Xor gating data to be transported from 1 slice to another
- Collaborated with pre-silicon validation engineers to define cluster-level directed/random tests, black box and white box test plan
- Defined performance scenarios for Arbiter blocks and FPV properties to validate the Arbitration policies using Jasper Gold
Component Design Engineer
Intel Corporation
01.2006 - 04.2009
- Responsibilities included implementation, execution, and debugging of the boot, CPD, and RC6 flow
- Worked on functional coverage coding, analysis, and identifying complex scenarios to fill up holes
- Enhanced product performance with thorough testing and validation processes
Verification Engineer Consultant
Makro Technologies Inc.
03.2005 - 01.2006
- Identified critical bugs through thorough regression testing, ensuring product reliability
- Developed comprehensive test cases to validate design specifications, increasing overall product quality
Education
Master of Science - Electrical Engineering
University of Texas At Arlington
Bachelor of Engineering - Electronics Engineering
University of Mumbai
Skills
- Project Leadership
- Problem-Solving
- Verilog
- Low-power Design
- RTL Design
- Memory Subsystem
- Jasper Gold FPV
- PTPX & Power Artist
- Static timing Analysis
Highlights
- An experienced engineer with over 18 years of experience in writing architecture specifications, RTL coding, defining verification plans, timing analysis, performance bottleneck analysis, and meeting power budgets, have been recognized by departmental awards for quality work at Intel.
- Apart from professional work, a passionate engineer who served as the Team Manager for the Destination Imagination team, which recently came in 10th at the Global Finals.
Timeline
Technical Lead/Manager
Intel Corporation
09.2022 - Current
Staff Design Engineer
Intel Corporation
09.2018 - 09.2022
Sr. Graphics Hardware Design Engineer
Intel Corporation
04.2013 - 09.2018
Sr. Design Engineer
Intel Corporation
04.2009 - 04.2013
Component Design Engineer
Intel Corporation
01.2006 - 04.2009
Verification Engineer Consultant
Makro Technologies Inc.
03.2005 - 01.2006
Master of Science - Electrical Engineering
University of Texas At Arlington
Bachelor of Engineering - Electronics Engineering
University of Mumbai