Ankita Verma
Santa Clara,CA
Summary
Principal Product Engineer with 13+ years of experience leading NPI projects from first silicon to HVM production. Expert in fab process optimization, test yield improvements, assembly yield enhancement, ATE characterization. Proven track record in cost-saving initiatives, cross-functional leadership. Seeking a challenging opportunity in cutting-edge semiconductor product engineering.
Overview
15
15
years of professional experience
Work History
Principal Product Engineer
Marvell Semiconductor
12.2022 - Current
- Led and launched an NPI project for a 16nm Automotive Ethernet product, successfully transitioning it from first silicon to mass production.
- Collaborated with Design Engineering to optimize nominal voltage (Vnom), ensuring AC and DC scan test coverage for slow-speed (SS) corner silicon at cold temperatures.
- Resolved HTOL failures by implementing Vkill for outliers at T0 during hot temperature insertion, driven by detailed data analysis of HTOL lots.
- Coordinated across design, test, DFT, and manufacturing teams to ensure a smooth production ramp.
- Drove continuous improvement culture in cross functional team to provide clear product design standards, improve manufacturability through enhanced documentation and reduce engineering cycle time.
Principal Product Engineer
ON Semiconductors Inc
01.2019 - 11.2022
- $400K cost saving achieved by ~8% yield improvement on latest BBIC product through PCIE test improvement in conjunction with TE and DFT teams
- Successfully launched latest baseband product in record time (3 weeks) after production test program completion
- Moved test hardware and material from engineering test location to production test location for data collection activity
- Presented CPK, GR&R, Test Documents, WAT vs FT Yield Analysis, Yield improvement DOEs to CAB committee to get approval from CFT including external manufacturing, QA teams
- Played pivotal role in selecting fab process corner so that both FT scan failure and standby current are minimized with fast scan clock
- Achieved $7.1M cost savings from yield improvement activities of flagship baseband and RF products
- 28nm HPC+ process parameter optimization DOE to transition from HPC platform to HPC+ platform for the latest BB product line
- Extensively worked on minimizing RF Gain Test & DC Offset fails by test HW optimization and LB site to site monitoring in production
- Spearheaded QTNA package BOM integration with ON Semi's Material BOM repository
- Leading 2 Product Engineers and mentoring PE's on NPI projects, assembly DOEs, BOM selection, fab process optimization
- Preparing cost analysis, deciding Tester Platform, Package Type for latest Flagship product for Client Project on 22FDx platform
SMTS Product Engineer
Quantenna Communications Inc
02.2019 - 05.2019
- Eliminated 15% OS fails of RF product caused due to bump non-wetting related failures by implementing mesh carrier for FCA reflow process and tightening substrate strip warpage at IQA
- Performed 15 Leg DOE to find the root cause and implement correct process reflow recipe
- Saved up to $1M by preventing high yield fallout from loadboard degradation
- Monitor test loadboard site to site variations on weekly/daily basis at each OSAT
- Successfully increased assembly yield of RF product from 95% to 99.2% by eliminating non-wetting related failures through DOE of flip chip process, substrate warpage control, mesh cover implementation
Senior Product Engineer
Quantenna Communications Inc
04.2016 - 02.2019
- Improved yield of BB product from 60% to 93% through PCM/WAT optimization and ATE limit relaxation
- Improvement in 28nm device baseline SBC from 150mA to < 90mA
- RF product yield improved from 63% to 92% through fab process parameter DOE and Test Limit Optimization
- Minimized VCO fails by 5%
- Spearheaded integration of YieldWerx (Yield Management System) with Quantenna's test, PCM, Genealogy and wafer sort files
- Monitor wafer SPC charts, CPK and create yield prediction models based on process parameter trends
Product Engineer
Quantenna Communications Inc
01.2015 - 04.2016
- Package Product Specification documentation of all QTNA products
- Failure Analysis and Resolution of a major manufacturing issue to ascertain if the issue originated in fab or in assembly
Assembly Product Engineer
Micron Technology Inc
07.2012 - 12.2014
- Successfully qualified new type of Package in Package (PIP) LGA product and managed product HVM ramp up
- Experience of leading cross functional team to resolve excursion issue and resume manufacturing
- Product management through subcontractor assembly sites in Asia (OSAT)
Research Assistant
Centre for Materials Research, Washington State University
08.2010 - 05.2012
- Hands on experience in photolithography, RIE, DRIE, plasma etching, Sputtering, oxidation, wet etching, SEM
- Successfully optimized process recipe for etching through wafer vias in Si wafers by cryogenic DRIE
Education
Master of Science - Materials Engineering
Washington State University
Pullman06-2012
Bachelor of Science - Instrumentation And Controls Engineering
Maharshi Dayanand University
Hayana, India07-2008
Skills
- Fab & Assembly Process Yield Improvement
- NPI & DFM Execution
- BOM Selection & Integration
- OSAT Assembly Qualification
- Fab Process Parameter DOE
- ATE Test Limit Optimization
- Yield Analysis Tools: JMP, Spotfire, Galaxy, Yieldwerx, Exensio, Dana
- Production Test HW Yield Monitoring
- SPC & CPK Monitoring
- Wafer Sort & TP Characterization Data Analysis
Timeline
Principal Product Engineer
Marvell Semiconductor
12.2022 - Current
SMTS Product Engineer
Quantenna Communications Inc
02.2019 - 05.2019
Principal Product Engineer
ON Semiconductors Inc
01.2019 - 11.2022
Senior Product Engineer
Quantenna Communications Inc
04.2016 - 02.2019
Product Engineer
Quantenna Communications Inc
01.2015 - 04.2016
Assembly Product Engineer
Micron Technology Inc
07.2012 - 12.2014
Research Assistant
Centre for Materials Research, Washington State University
08.2010 - 05.2012
Master of Science - Materials Engineering
Washington State University
Bachelor of Science - Instrumentation And Controls Engineering
Maharshi Dayanand University
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