Anubhav Jain

• Designed and developed ATIP, an ASIC screening tool that accelerated screening time by ten times, significantly enhancing Cisco’s revenue by reducing time-to-market.
• Functionally managed global collaboration across teams in India, China, Taiwan, and USA to optimize ASIC screening processes.
• Directed release planning and quality assurance for diagnostics, manufacturing, and software teams, ensuring timely product rollouts of high quality.
• Maintained and enhanced Cisco's ASIC SDKs, driving major revenue streams for critical customer-facing products.
• Led cross-functional debugging efforts among applications, software, and hardware teams to deliver real-time fixes for critical customer issues.
• Completed various training sessions on AI applications relevant to work, including AI Inference Infrastructure summit and Byte-Sized ML Beginner Series.

Acquired knowledge of NSIM/DSIM test infrastructure for Palladium and basic design of TM block and FLLB block of GR3.

Implemented HW-NPL model for both blocks and tested code for compilation errors.

• Developed and optimized APIs for Cisco's networking ASICs, ensuring seamless integration with existing SDK frameworks.
• Spearheaded debugging and issue resolution, resolving complex hardware-software integration challenges to ensure stable and efficient operation.
• Designed and executed comprehensive initialization and test procedures to transition ASICs into production environments successfully.
• Partnered with architects, developers, and ASIC design teams to solve complex issues, enhancing system reliability and scalability.

Developed SoftWare behavioural Model for beverly and

Quadpeaks. It acts like a golden reference to accelerate

the development of upper layers, development of RTL and

development of verification test bench.

Developed P4 Language compiler in Java using ANTLR

framework. It compiles the p4 program and generate the

configuration as per Hardware architecture.

• Developed software behavioral models for ASICs, serving as golden references for upper-layer development, RTL creation, and test bench verification.
• Built a P4 language compiler in Java using the ANTLR framework, enabling configuration generation aligned with hardware architecture.

• Upgraded eMMC and SD host controller drivers to support HS200/HS400 speed modes.

Implemented command queue and FFU features to enhance data access performance.

Modified kernel to integrate advanced features for improved storage efficiency.

Upstreamed changes to maintain alignment with open-source standards.

Focused on development of storage variants including eMMC and SD.

• Developed mobile applications, web services, and databases to manage disaster information systems effectively.
• Delivered innovative solutions that streamlined data handling and improved response times during critical scenarios.