Anuja Shah
MILPITAS,CA
Summary
Competent Engineering professional offering foundation in engineering project management and design. Detail-oriented, organized, Works at fast pace to meet tight deadlines.Ability to handle multiple projects simultaneously with a high degree of accuracy.
Overview
9
9
years of professional experience
Work History
IP Logic Design Engineer
Intel Corporation
12.2021 - Current
- Developed positive working relationships with stakeholders to effectively coordinate work activities.
- Achieved successful project outcomes by maintaining accurate documentation and meeting strict deadlines.
- Optimized engineering processes by implementing innovative solutions and streamlining workflow.
- Conducted rigorous quality assurance tests, identifying areas of improvement for product optimization.
- Conducted feasibility studies for new projects, providing detailed analysis and recommendations that informed leadership decisions.
FPGA Prototyping Engineer
Intel Corporation
11.2017 - 12.2021
- Established strong working relationships with clients through exceptional communication skills, fostering trust and collaboration.
- Wrote, reviewed and edited technical document in accordance with template requirements.
- FPGA based prototyping for wireless systems: instrumental in defining and integrating RTLFPGA top, Qsys/IP integration, taking the FPGA design through synthesis, place and routeand bit file generation and timing closure. Enhanced the build quality/build time throughdifferent optimization techniques.• Built test infrastructure, writing testcases, functional FPGA / IP Validation.• Pre-silicon verification for digital design and Mixed signals verification: involved in buildingsimulation infrastructure, testbench, writing testcases, functional verification, working withBFM’s and VIP’s, Qsys based simulation, coverage
Research Scientist
Intel Corporation
07.2015 - 12.2017
- Utilized expertise in microbiology, chemistry, and hematology to help with diagnosis of medical issues.
- Streamlined research processes to meet tight deadlines for multiple projects.
- Designed a board for a test chip, PO readiness plan, developing hw/sw programs for unit,cluster, and full chip testing.• Participated in developing POC for self- interference cancellation using bilinear core byleading an effort to emulate the IP, integrate it with other subsystems and resolveintegration and timing and place/route issue on the FPGA.• Research: Configurable FFT’s structures for LTE- developed Matlab framework to evaluatedifferent LTE configurations for Area/power/latency and memory requirement. Also,explored methodology to generate memory blocks using GenRam to analyze leakagepower and area.
Education
Master of Science - Computer Engineering
Portland State University
Portland, OR06.2015
Skills
Hardware Languages: Verilog, System Verilog EDA tools: Xilinx: ISE - Vivado, Altera: Quartus, VCS, Modelsim, Verdi, Cadence- Schematic, Virtuoso, DCcompiler Scripting Languages: TCL, Python, UNIX shell scripting Programing language: Assembly Language (8085/8086, 8051&PIC-18, KCPSM6) Bench Equipment’s: Oscilloscopes, Spectrum Analyzers, logic analyzers, NI PXIe-6544 and Power supplies
- Engineering Documentation
Accomplishments
Was awarded with several Division Recognitions award for my contribution towards POC, Tape outs and Verification/Validation Effort across different projects.
One of Inventor for US patent on RLS- DCD Adaptation hardware accelerator for interference cancellation in Full- Duplex Wireless systems (9935615) and energy efficient polynomial kernel generation full duplex radio communication (9893746 B2).
Culture: I am a strong team player, doesn’t shy away to work with cross domain teams, excellent communication skills and flexible.
Timeline
IP Logic Design Engineer
Intel Corporation
12.2021 - Current
FPGA Prototyping Engineer
Intel Corporation
11.2017 - 12.2021
Research Scientist
Intel Corporation
07.2015 - 12.2017
Master of Science - Computer Engineering
Portland State University
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