Summary
Overview
Work History
Education
Skills
Timeline
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APHOORVA SANGARAJU VENKATA

Summary

ASIC verification engineer with 9 years of experience, expertise in System Verilog and UVM based verification environment setup. I am looking forward to learn and take more responsibilities to achieve organization objectives.

Overview

9
9
years of professional experience

Work History

Member of Technical Staff

Invecas Technologies Pvt. Ltd
02.2020 - 08.2021
  • Worked for client: Synopsys, Inc.
  • Provide a root cause analysis for the client design, identify possible issues, and verify the Registered Transfer Level (RTL) with the required test-bench updates.
  • Analyze the product design and suggest possible improvements for better customer standards and also ensure backwards compatibility for existing features
  • Worked on Automatic Test Equipment (ATE) Simulations, analyze and debug the simulation results
  • Perform thorough regression testing for the changes and new features to ensure a bug-free product delivery to the customers
  • Improve the test cases for all added scenarios and maintain overall test coverage above 95% before handoff

Senior Verification Engineer

Soctronics Technologies Pvt. Ltd
07.2014 - 01.2020
  • Worked for clients: AMD, Invecas Technologies Pvt. Ltd.
  • Worked on context switching, Rx-Duty Cycle Correction (Rx-DCC), Tx-Duty Cycle Correction (Tx-DCC), VCO calibration, loopback modes, and user-defined transmission features for SERDES 25G verification using SystemVerilog and UVM.
  • Test the product provided by the design team and perform thorough regression as per the assigned specification
  • Report and assign any identified issues back to the design team for debugging and resolve them
  • Coded System Verilog assertions to check and keep track of Rx and Tx clocks duty cycles in the UVM testbench
  • Added checkers to check the transmitted and received user-defined data on parallel and serial interface respectively
  • Run SDF simulations
  • Created testcases to verify the KX, KX4, KR and KR4 and EEE modes for Ethernet
  • Identified and debugged issues, contributing to the refinement of the design and verification environment
  • Verified VIP test suites and meticulously tested error scenarios to ensure robust and reliable design behavior
  • Verified AN for all the modes and AD in KR
  • Verified Debug bus through assertions for the in-house testchip
  • Debugged verification failures, reported bugs to the design team, and ensured RTL fixes were implemented without impacting the integrity of the overall design
  • Verified the Ethernet testchip integrated with 'More Than IP' controller and internal mac IP
  • Provide test cases for all regression scenarios as per the provided specification
  • Improve code coverage and functional coverages after the design improvements and updates
  • Provide detailed knowledge transfer about the product specifications, regression scenarios, and test case scenarios before the product handoff to the client.
  • Report back any identified issues from the client, if any, to the design team to address them with utmost priority.

Verification Engineer

Davinci Nanotech Private Limited
07.2012 - 06.2014
  • Worked for Client: Ineda Systems Pvt. Ltd.
  • Created new test cases to verify the data path in the 13-port switch and the scheduler in the switch.
  • Run the test cases for various bandwidths to check the switch operations by programming the token buckets in the scheduler.
  • The datapath was checked for various random scenarios by coding new test cases.
  • Responsible for testing and debugging the functionality of the design and report the bugs to the design team
  • Various arbitration methods, such as round robin, Strict Priority, DRR, and WRR, designed for the scheduler, were verified by coding direct test cases and random test cases.
  • Developed and updated the testbench components whenever new changes were done in RTL
  • Responsible for improving and closure of code coverage and functional coverage
  • Developed checker block for the testbench and used efficient algorithms and data structures in the checker block
  • Testcases were coded to verify the Rx transactions through AXI bus for the VNIC block.

Education

Masters of Science - Electrical Engineering

University of Texas
Arlington
05.2024

Bachelor of Engineering - Electrical and Electronics Engineering

Anna University
Chennai, India
05.2011

Skills

  • UVM
  • System Verilog
  • Verilog
  • C
  • C
  • Coverage Closure
  • SERDES
  • ETHERNET
  • AXI
  • DDR
  • NCSim
  • VCS
  • VERDI
  • QuestaSim
  • DVE
  • Windows
  • Linux

Timeline

Member of Technical Staff

Invecas Technologies Pvt. Ltd
02.2020 - 08.2021

Senior Verification Engineer

Soctronics Technologies Pvt. Ltd
07.2014 - 01.2020

Verification Engineer

Davinci Nanotech Private Limited
07.2012 - 06.2014

Masters of Science - Electrical Engineering

University of Texas

Bachelor of Engineering - Electrical and Electronics Engineering

Anna University

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