Apoorva Reddy Proddutoori
San Diego,CA
Overview
5
5
years of professional experience
Work History
Post Si Power Engineer
Qualcomm Technologies, Inc.
11.2021 - Current
- Mobile device competitive analysis for performance, power and architecture
- Developed tools to profile power breakdown for video playback analysis on android and iOS to understand DCVS and lower GPU consumption
- Constructed experiments basen on voltage scaling to analyze performance, power and bandwidth of CPU/GPU
- Formulated DDR bandwidth utilization for Aztec Ruins Vulkan on android targets
- Camera subsystem power competitive analysis
Hardware Engineer
Qualcomm Technology Inc.
06.2020 - 11.2021
- Generated flow for post silicon functional verification and low power application in Smartest to check DC and Vmin across PVT
- Implemented Qualcomm's Autophasing UI tool to validate test data and generate Fmax/Vmin Schmoo to evaluate test patterns at corner cases
- Validated DC connections on the Chip, Loadboard and Tester
- Created ATE Testflow to modify Levels/Timings to check working of JTAG
- Improved the Yield by optimizing test patterns to reduce the Test time and ultimately reach steady state
Research Assistant
ASU - Standardization of 5nm library cells on a predictive PDK (ASAP5 PDK)
01.2019 - 06.2020
- Static Timing Analysis and Layout of 5nm library cells using Cadence Virtuoso and Innovus
- Optimizing the power, area and timing by making the design more robust.
Education
Master of Science - Computer Engineering
Arizona State University
Tempe, AZ05.2020
Master of Technology - Communication and Signal Processing
Jawaharlal Nehru Technological University
05.2018
Bachelor of Technology - Electronics and Communication Engineering
Jawaharlal Nehru Technological University
Skills
- SVN
- JIRA
- Agile
- Python
Projects
- RTL to GDSII implementation of 64-bit RISC-V Microarchitecture Implementation - Designing a 64-bit RISC-V single cycle processor in System Verilog and Perl using Genesis 2., Designed system verilog modules for ALU, Priority Encoder, LIFO, FIFO, Shift Register, Sequential Multiplier, Sequential Divider, Sequential Square root, Fair Arbiter and Integrator on Genesis 2. And optimized the designs for minimum Delay, Power and Area.
- Implementation, Optimization and Performance analysis of AES Algorithm on FPGA - Implemented the 128-bit data and 256-bit key respectively using AES algorithm on Xilinx Zynq ZCU 102 board using Verilog., Performed pipelining optimization technique to increase the throughput per watt restricting the power to 100mW.
- RTL to GDSII Implementation of Convolutional Neural Network using 7nm technology - Designed and Verified CNN Max-pooling Engine using System Verilog, Synthesized the design using Synopsys DC Compiler., Performed complete ASIC design flow i.e., RTL and Gate Level Netlist Synthesis using ModelSim, Floor Planning, APR, Clock Tree Synthesis using Cadence Innovus, Post Layout timing analysis and Power analysis using Primetime. And Optimized for latency. ASIC Design Implementation of 2-bit adder
- 16:1 MUX using 7nm FINFETPDK - Developed RTL model using Verilog, functionality verification using ModelSim, Performed synthesis using DC compiler and performed ASIC design flow. Physical Design of 16 word 16-bit register file with 1 read and 1 write port using 7nm ASAP7 PDK, Spring 2019, Designed and optimized full custom 16 entries, 16-bit wide dynamic register [8T SRAM] using a 4x16 and a 3x8 decoder., Performed DRC and LVS; verified functionality of obtained PEX netlist and performed static timing analysis using HSPICE.
- Tool Driver and Circuit Simulator Scripting using PYTHON - Developed a python script to determine the optimal size and number of stages in an inverter chain for specific load., Developed a circuit simulator to perform nodal analysis on circuits with independent and dependent current sources.
Timeline
Post Si Power Engineer
Qualcomm Technologies, Inc.
11.2021 - Current
Hardware Engineer
Qualcomm Technology Inc.
06.2020 - 11.2021
Research Assistant
ASU - Standardization of 5nm library cells on a predictive PDK (ASAP5 PDK)
01.2019 - 06.2020
Master of Science - Computer Engineering
Arizona State University
Master of Technology - Communication and Signal Processing
Jawaharlal Nehru Technological University
Bachelor of Technology - Electronics and Communication Engineering
Jawaharlal Nehru Technological University
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