Aravind Veginati

As a master's student, I'm seeking a job in FPGA development and VLSI design job. competent in FPGA implementation (HDL, floorplanning, optimization), signoff verification (DRC/LVS, power, timing), and translating RTL to optimized layouts. competent in Verilog/VHDL and Cadence tools. strong problem-solving, communication, and problem-solving abilities. eager to share my knowledge and enthusiasm for chip design.

• Cadence RTL-to-GDSII Flow v5.0, Identify the concepts from all the stages of RTL2GDSII flow
• Virtuoso Schematic Editor vIC6.1.8/ICADVM20.1, Create and edit schematics with Virtuoso Schematic Editor
• Innovus Block Implementation with Stylus Common UI v22.1, Use the Innovus Implementation System software with Stylus Common UI
• Innovus Hierarchical Implementation with Stylus Common UI v22.1, Use floorplanning and create partitions for your design
• Basic Static Timing Analysis v2.0, Identify the basic concepts of static timing analysis

DATA ENCRYPTION USING HARDWARE MODELLING BASED ON RSA WITH PUF : 

Propose an IP paradigm for RSA-based encryption, tools used: Cadence Digital Design Implementation tools.

Research and Design of a High-Security Configurable RO-PUF Based on FPGA : 

Propose a Reconfigurable RO-PUF, tools used Xilinx Vivado. 

Smart Street Light Control system, Monitor and control street lights:

tools used: Proteus 8, Arduino Ide.