ARRTHI SHANMUGARAJU
Santa Clara,USA
Summary
Adaptable professional with a quick-learning ability and a talent for adjusting to new environments. Skilled in rapidly acquiring new knowledge and applying it effectively. Driven by a passion for continuous learning and successfully navigating change.
Overview
8
8
years of professional experience
1
1
Certification
Work History
DFT Design Engineer
Altran
Bengaluru, India
10.2016 - 12.2019
- Company Overview: Client: Intel (Bengaluru India)
- Worked on DFT logic design and integration, MBIST insertion & verification and scan for different IPs
- Implemented various RTL changes required for implementing MBIST insertion
- Implemented MBIST controllers to achieve high fault coverage with minimal area and power overhead
- Collaborated with design, verification to integrate and validate MBIST
- Generated and verified test patterns for at-speed testing and fault isolation in embedded memories
- Worked on scan implementation and Memory BIST to test manufacturing faults across projects
- Hands on experience on Zero Delay and Timing based (SDF) Simulations and debug
- Client: Intel (Bengaluru India)
Career Break
CERTIFICATION
01.2020 - 12.2024
- Relocated to the United States and completed the necessary legal and immigration processes, including obtaining an Employment Authorization Document (EAD).
- Proactively pursued DFT courses to stay updated with the latest industry trends, and enhance technical proficiency.
- Engaged in continuous learning through courses and industry research.
Education
Master of Engineering - VLSI design
SSN College of Engineering
Chennai, India06.2016
Bachelor of Engineering - Electrical and Electronics Engineering
Thangavelu Engineering College
Chennai, India06.2014
Skills
- ASIC design flow
- RTL design
- Post silicon bring up
- Low power DFT
- Hierarchical DFT
- IEEE 11491
- IEEE 1500
- Fault models
- MemoryBist
- BIRA
- ATPG
- Test compression
- Verilog
- System Verilog
- Perl
- TCL
- Tessent /LV MBIST flow
- SpyGlass DFT
- Synopsys Design Compiler
- Tetramax
- Novas Verdi
- Mentor Graphics DFT Visualizer
Certification
Design for Testability (DFT) Certification, 12/01/24, Completed an in-depth course covering DFT concepts, tools, and techniques for improving the testability of integrated circuits and systems. Gained hands-on experience with DFT methods, including scan chains, boundary scan, BIST, and test coverage optimization.
Publications
TUNNELFET BASED FLASH MEMORY USING JUNCTIONLESS DEVICE, SSN College of Engineering, 2016
Personal Information
Visa Status: H4 EAD
Timeline
Career Break
CERTIFICATION
01.2020 - 12.2024
DFT Design Engineer
Altran
10.2016 - 12.2019
Master of Engineering - VLSI design
SSN College of Engineering
Bachelor of Engineering - Electrical and Electronics Engineering
Thangavelu Engineering College
Similar Profiles
Sachin DeoraSachin Deora
Salesforce Administrator at AltranSalesforce Administrator at Altran
Elie METAYERElie METAYER
Leader Qualité at Altran / Capgemini EngineeringLeader Qualité at Altran / Capgemini Engineering
Sudha NSudha N
Consultant at Altran Technologies India Pvt Ltd (Part of Capgemini)Consultant at Altran Technologies India Pvt Ltd (Part of Capgemini)