Summary
Overview
Work History
Education
Skills
Accomplishments
Timeline
Generic

Arun Prasad Tambrahalli

Sr Emulation Engineer
Mountain View,CA

Summary

Principal Emulation & Post-Silicon Validation Engineer with 18 years of experience steering System-on-Chip development from concept to commercialization. As a founding member of the Emulation & Silicon Validation team, developed the comprehensive framework for all IP and SoC emulation & FPGA prototyping flows, driving key evaluation decisions and contributing to patented technologies that shaped product success. Instrumental in the commercialization of 3 generations of Mobile & Data centre SoCs.

Overview

18
18
years of professional experience

Work History

Emulation Lead

Google
10.2024 - Current
  • Engineered and implemented a DVFS emulation solution to validate complex, HLOS-driven power and performance use cases during the pre-silicon development phase.
  • Co-invented and currently deploying a patented technology that accelerates emulation speed by up to 3x through novel enable extraction and asynchronous clocking techniques.
  • Driving the creation of a combined emulation and prototyping workflow for Zebu 5 and HAPS-200 systems.
  • Accelerated validation and software development by enhancing emulation model quality; partnered with verification team to integrate critical performance and low-power scenarios into bare metal testing.
  • Authoring a design concept for a hybrid verification flow using AssertLLM and AssertionForge & DPI to implement formal verification with SV assertions in emulation, aimed at improving the quality and coverage of pre-silicon testing

Emulation Lead

Google
10.2023 - 05.2025
  • Designed, developed, and deployed a highly scalable and reconfigurable multi-threaded emulation test bench, designed to support varying SoC interface configurations for multi-generational product roadmaps.
  • Developed a multi-chip emulation solution for an integrated Tensor SoC and PMIC, introducing a design partitioning method that simplified implementation and accelerated system-level validation.
  • Enabled real-world device validation by successfully implementing a PCIe Gen 4 speed bridge, which interfaced the emulated SoC with a commercial WiFi card for interoperability testing.
  • Leveraged AI to convert a verification environment's low-power state checker into a DPI based synthesizable transactor, streamlining the debug of intricate power management issues
  • Created a Bare-Metal regression framework to speed up emulation testing, directly contributing to a 1-2 week improvement in the overall Emulation Model release process.
  • Deployed a framework to Simulate Emulation Infrastructure before Compile with SEM Flow

Emulation Lead

Google
08.2022 - 09.2024
  • As a founding member of the Emulation team, architected the initial runtime infrastructure for Google's first fully custom chip (Tensor G5) from scratch, enabling a record-setting 4-day silicon bring-up to a full Android boot
  • Partnered with Front-End CAD to implement a new automated emulation build workflow, training 12 engineers and reducing build preparation time from 1 week to 1 day
  • Accelerated emulation boot and testing cycles by developing a versatile Python/TCL framework for preloading a diverse range of SoC memories
  • Achieved first-pass silicon success for the Tensor A1 audio chip by pioneering a hybrid Emulation and ProFPGA-based validation strategy, enabling end-to-end testing with real-time audio equipment pre-silicon

Emulation Engineer

Google
07.2021 - 09.2022
  • Developed a Novel IP Hybrid platform for accelerated development of TPUv3 & Tensilica DSP for early pre-silicon validation and driver development.
  • Developed Palladium based ACE-Lite and AXI Transactor-based infrastructure to implement ASIC Netlist of Imagination Mobile GPU on a Pre-Silicon platform for Power Estimation & Performance Analysis, resulting in upgraded GPUs being chosen for Next Generation Google Tensor SoCs.
  • Interfaced with IT to enable Jenkins-based Continuous Integration flow for Silicon Software teams.
  • Planned Pre-Silicon Power Estimation for various IPs and System scenarios using Synopsys tools.
  • Supported Volume Testing, Voltage characterization & Silicon Power Measurements for GPU and DSP IPs.

Emulation & Validation Engineer

Google
01.2020 - 09.2021
  • Developed HAPS & ProFPGA based FPGA Prototyping solution for Quad core DSP IP getting to Pixel 22 SoC.
  • Developed & Deployed a Hybrid Zebu Emulation Solution with ARM Fast model & Synopsys Virtualizer for Quad Core DSP for end-to-end Software development.
  • Owned Functional, Power and Performance Validation of Mali 700 GPU IP & Tensilica DSP.
  • Supported Volume Testing, Voltage characterization & Silicon Power Measurements for GPU and DSP IPs.

System Validation Lead

Qualcomm India Pvt Ltd, Bangalore
01.2018 - 01.2020
  • Led System Validation for SDM720, overseeing validation of Qualcomm’s first Mid-Tier SOC with premium features, including an integrated 5G Modem and an AI subsystem for on-device AI.
  • Implemented tests to measure 4G and 5G use case power and report possible optimizations.
  • Trained & Mentored new team members on Emulation Flows and Validation environments.

System Validation Engineer/Emulation Lead

Qualcomm India Pvt Ltd, Bangalore
12.2014 - 12.2017
  • Enabled full-chip validation of a 24-core AI inference SoC by engineering a novel multi-system platform, linking 4 RUMI units with a custom integration that overcame performance bottlenecks inherent in a chained-emulator setup
  • Led FPGA Emulation for Qualcomm’s first 5G Modem-Based SoC, interfacing with global teams to deliver a high-intensity project that resulted in the first 5G solution.
  • Created Detailed User Equipment (UE) Emulated on FPGA Platform to Test Base Station (TBS) Digital interface specification for both mmWave and Sub6.
  • Developed RTL code for a new interface wrapper to provide a complete End-to-End Emulation Platform.
  • Conducted Synthesis Timing closure for the entire SoC.
  • Performed Post-Silicon activities, including Chip Bring-up, Hardware Validation, and identifying critical Silicon Bugs.


System Validation/Emulation Engineer

Qualcomm India Pvt Ltd, Bangalore
12.2011 - 12.2014
  • Performed Emulation and Hardware Validation of new software-defined Modems for Low & Value Tier smartphones.
  • Interacted with Modem Systems and Design Teams for test case creation.
  • Enabled Power Measurement for a new IP block and correlated with Verification Team’s power measurement numbers.
  • Contributed to different Emulation and Validation activities on above chipsets.

IP Validation/Emulation Engineer

Synopsys/Haritsa Design Automation, Bangalore
08.2007 - 11.2011
  • Directed and Constraint Random Verification for Functional and Code Coverage for USB3.0 and USB2.0 IP.
  • Prepared the IP for FPGA Prototyping and performed Synthesis Timing Closure.
  • Brought up the HAPS51T Board.
  • Performed Software setup including Linux Kernel & DWC_USB3.0 & DWC_USB2.0 Device Driver debugging.
  • Conducted OTG2.0 Protocol and Hibernation feature Validation Tests for Design ware USB IPs.

Education

Post Graduate Diploma - VLSI

C-DAC
08-2007

Bachelor of Engineering - Electronics and Communication

Visvesvaraya Technological University
10-2006

Skills

CPU: ARM V9/V8 CPUs, Qualcomm QDSP 5x, QDSP 6x

Accomplishments

Patents & Awards
  • Contributor to Patent US81153951: Enable extraction and MCP computation from clock cone logic driven by multiple primary clocks.
  • Super Qualstar: Enabling Tapeout of first 5G NR System-on-Chip in record 7 months.

Timeline

Emulation Lead

Google
10.2024 - Current

Emulation Lead

Google
10.2023 - 05.2025

Emulation Lead

Google
08.2022 - 09.2024

Emulation Engineer

Google
07.2021 - 09.2022

Emulation & Validation Engineer

Google
01.2020 - 09.2021

System Validation Lead

Qualcomm India Pvt Ltd, Bangalore
01.2018 - 01.2020

System Validation Engineer/Emulation Lead

Qualcomm India Pvt Ltd, Bangalore
12.2014 - 12.2017

System Validation/Emulation Engineer

Qualcomm India Pvt Ltd, Bangalore
12.2011 - 12.2014

IP Validation/Emulation Engineer

Synopsys/Haritsa Design Automation, Bangalore
08.2007 - 11.2011

Post Graduate Diploma - VLSI

C-DAC

Bachelor of Engineering - Electronics and Communication

Visvesvaraya Technological University
Arun Prasad TambrahalliSr Emulation Engineer