Asritha Chowdary Chunduri
Austin,USA
Summary
Physical Design Engineer with deep expertise in implementation, STA, and PPA optimization, delivering multiple successful tapeouts.
Overview
7
7
years of professional experience
Work History
Senior Physical Design Engineer
Microsoft
Austin, USA
12.2025 - Current
- Owned Synthesis and backend implementation of compute blocks within Server SOC.
- Led timing closure efforts, conducting what-if analysis on critical path buckets to understand timing bottlenecks and guide optimization strategies for downstream implementation.
- Performed detailed PPA investigations, partnering with RTL and DFT teams based on shifts observed across milestones.
- Built an AI-driven constraint checking tool to accelerate design convergence, reducing manual iteration time.
SOC PD Timing Engineer
Apple Inc.
Austin, USA
12.2020 - 12.2025
- Responsible for STA closure at the SOC level, involving complex multi-voltage domains.
- Experience with critical high-speed interface convergence requiring special construction handling.
- Led final signoff convergence checks - including DRV and signal analysis checks, and directed ECOs to guide timing convergence.
- Managed budgeting and uncertainty flows at the SOC level, pushing down context information to accelerate interface convergence.
- Developed and maintained extensive PrimeTime flows supporting successful tapeout and robust silicon performance.
Component Design Engineer
Intel Corp.
Hillsboro, USA
08.2019 - 12.2020
- Worked on a 7nm Register File, 2R2W port memory compiler operating from 1.3-3 GHz across various memory sizes, at 0.65V, 100C.
- Responsible for memory power characterization and contributed to a scaling model used to populate results for all other IP flavors.
- Proficient in Tcl; developed netlist code for macros used in the tiling of a memory IP.
Education
Master of Science - Computer Engineering
Arizona State University
Tempe, AZ05-2019
Skills
- PrimeTime
- Fusion Compiler
- Innovus
- Tempus
- HSPICE
- Cadence Virtuoso
- Tcl / Perl / Python
Timeline
Senior Physical Design Engineer
Microsoft
12.2025 - Current
SOC PD Timing Engineer
Apple Inc.
12.2020 - 12.2025
Component Design Engineer
Intel Corp.
08.2019 - 12.2020
Master of Science - Computer Engineering
Arizona State University