Avijit Dutta
Portland,OR
Summary
Dynamic architect with extensive experience at Cadence Design Systems, specializing in EDA optimization algorithms for physical and logical synthesis. Proven track record in power optimization and design efficiency, complemented by strong leadership in advanced semiconductor systems. Adept at leveraging ML applications to drive innovation while fostering collaborative team environments.
Overview
26
26
years of professional experience
1
1
Certification
Work History
Architect
Cadence Design Systems
Portland, United States
07.2018 - Current
Datapath optimization
· Carry-save optimization (CSA)
· Maximal CSA
· Power aware CSA/datapath
High level optimization
Congestion aware synthesis / physical synthesis
Physically driven MUX clustering for congestion
Physically aware load clustering
Power optimization
· Word level shannon transformation
Structuring Optimization
Senior Staff
Synopsys
Portland, United States
05.2013 - 07.2018
· Logic/Physical synthesis heuristics/algorithms
· Constrained optimization in the areas of low power/delay/area
Principal Engineer
Cypress Semiconductor
Portland, Oregon
08.2011 - 05.2013
- Led architectural design for advanced semiconductor systems with a focus on power optimization and performance.
- Conducted extensive research on programmable system-on-chip (PSoC) architectures to enhance design efficiency.
Technical lead
Mentor Graphics
05.2007 - 07.2011
- R&D in the areas of ATPG, DFT, Compression.
Member of Technical Staff
Cadence Design Systems
06.2000 - 03.2003
- Worked on verilog simulators and VHDL simulator interfaces
Education
Machine Learning
Stanford University
03.2023
Doctor of Philosophy (Ph.D.) - Electrical and Computer Engineering
The University of Texas at Austin
Master of Science (MS) - Electrical and Computer Engineering
The University of Texas at Austin
Bachelor's Degree - Computer Science
Jadavpur University
Skills
- EDA optimization algorithms in the areas of physical and logical synthesis
- Design for Test architectures and algorithms
- ML basics and applications
Certification
Machine Learning
Awards
- Special Achievement Award
- Excellence Award
- Recognition Award
- Exceed customer expectations award
Publications
- Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code.
- Iterative OPDD Based Signal Probability Calculation.
- Partial Functional Manipulation Based Wirelength Minimization.
- Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code.
- Synthesis of nonintrusive concurrent error detection using an even error detecting function.
Personal Information
Title: Architect at Cadence Design Systems
Patents
Low cost adjacent double error correcting code
Timeline
Architect
Cadence Design Systems
07.2018 - Current
Senior Staff
Synopsys
05.2013 - 07.2018
Principal Engineer
Cypress Semiconductor
08.2011 - 05.2013
Technical lead
Mentor Graphics
05.2007 - 07.2011
Member of Technical Staff
Cadence Design Systems
06.2000 - 03.2003
Machine Learning
Stanford University
Doctor of Philosophy (Ph.D.) - Electrical and Computer Engineering
The University of Texas at Austin
Master of Science (MS) - Electrical and Computer Engineering
The University of Texas at Austin
Bachelor's Degree - Computer Science
Jadavpur University