Summary
Overview
Work History
Education
Skills
Websites
Workauthorization
Personal Information
Timeline
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Balasubramaniam Gopal

San Ramon,USA

Summary

24+ years of experience in RTL Design, SoC Integration, DFT, Verification, Silicon Bring up

Overview

24
24
years of professional experience

Work History

Sr DFX Engineer

Intel
Santa Clara
04.2021 - Current
  • Implemented centralized setup for the Scan Fabric (SSN) ATPG flow for 36+ Unique partitions, Deliver Cell-Aware Patterns. Similarly, streamlined MBIST pattern generation workflow across partitions
  • Implemented Tessent TCL automation to produce comprehensive BSCAN collaterals, encompassing a scan cell report and its corresponding BSCAN Shadow/capture register
  • Developed custom perl script to generate Multi-die Package BSDL and BSCAN Patterns, facilitating pre and post silicon validation. Mutidie TAP & Scan Fabric BFM integration into the validation environment, implemented the multi-die DFT test plan and validation

Sr Staff Engineer

Synaptics
San Jose
09.2018 - 04.2021
  • Implemented Tessent MBIST and automated ARM shared-bus MBIST for improved efficiency, SCAN/ATPG and Verification for BG6, BG7 DFT(set top box, 12nm), DisplayLink (Dock on a Chip) chips
  • Memory generation wrapper (perl) script for PPA targets across the different memory compilers. RTL-MBIST flow automation and integration with functional RTL, Verification to enable DV and MBIST tests, filelist modifications for synthesis and design validation, desSync version control automation
  • Generated memory repair collateral using Tessent TCL scripting, mapped it with MBIST test cycles, and integrated it into the ATE testmethod.

Sr Staff Engineer

Qualcomm
San Diego
11.2011 - 09.2018
  • Implemented clock staggering techniques that resulted in a remarkable improvement of 6 to 17% in the frequency of SCAN shifts for Aragorn SCAN (28nm).
  • Implemented and verified SoC LVmemBIST for Gandalf (28nm), Istari (14nm), Nazgul (10nm), and Hana (7nm). Enhanced tool generated MBIST RTL Code for LPDDR2 DRAM LVMEMBIST (14nm) by incorporating re-configurable features to support various frequency algorithms.
  • Enhanced LVmemBIST process by incorporating the central MBIST through CTS Aware techniques using LVSCAN models. Flow flushed the clearcase version control across 23 clearcase projects. Implemented concurrent execution of MBIST to decrease test duration. Implemented the ATE test cycle mapping to enhance the failure analysis processes. Enhanced functional clock drivers to enable re-use of memory clock domains across MBIST tests.

Consultant

Synapse DA (Client: STE, Broadcom, TI)
Bangalore
09.2008 - 11.2011
  • DFT (Scan, ATPG, MBIST) Specification, Implementation, Verification across the STE G2848 SOC (45nm), STE U3600 SOC (45nm) projections
  • BRCM Mercury IC (45nm): ARM11, DSP LVmemBIST, LBIST DFT Spec to vector deliverables
  • TI-India GAIA IC (60nm): ATPG/PBIST Vectors verification, hardware accelerator activities
  • TI-France Scorpio (45nm): Implement Clock & reset structures and integrate with the PBIST, IEEE1500 Controller, BSR logic using Autogen RTL integration. Interface with customer team members to drive and align on the TI-DFT guidelines

Technical Leader

NXP
Bangalore
09.2006 - 09.2008
  • Coala (AmbiLight-TV, 120nm): DFT Architecture, DFT RTL structures coding in collaboration with NXP Eindhoven DFT team, AMS Test isolation and hookups, vector generation, verification. Scan insertion, ATPG, MBIST Integration/Patterns PNX8306T (Set top box, 65nm). ATE test support for Apollo IC (45nm) in collaboration with NXP-Germany mentors. Memory RMA debug resolution on Benbrook IC (60nm).

Sr Design Engineer

Texas Instruments
Bangalore
05.2004 - 09.2006
  • Scan, MBIST, ATPG activities for Modem DFT (45nm), HAN PBIST (45nm), ARMSS9, ARMSS11, DSPSS subsystems
  • IEEE1500 Master, Slave Test Access Module RTL automation, DFT TAP, BSD integration for Hacker (45nm),
  • Developed a customized Perl script to generate Switch Fabric RTL and make modifications to customer netlist by inserting PBIST and Switch fabric components along with memory connections.
  • OMAP4X (45nm): 25+ Wireless RTL IPs with Fault Coverage enhancements of > 99.5%, DC DFT DRC Classifier, ATPG Fault Analyzer, Scan Failure-Verilog, PLI, eFuse chain integrity validation testbench, automation in shift TDL power characterization through VCD
  • DFT consultant for the DFT specification & review across the design UMA31, GFX_OMAP3430, HAN, HAWKEYE, Maserati1, Spitfire2 DFT Specification

Design Engineer

HCL Technologies
Chennai
09.2000 - 01.2003
  • Thread Controller: Implemented an efficient hardware engine specifically for the software post-processing (ARC-CPU) of Serial/Parallel requestors. Configured Lex Action Engine to arbitrate LEXER CPU and implemented parallel hardware threads. Arbitrated Parse Action Engine with PARSER CPU and configurable serial hardware threads. Integration of DMA, round-robin arbitration logic with ARC-CPU. Debug access control logic implementation based on firm-ware requirements Unit & SoC Verification: Perform unit level verification and involved in the SoC verification support & review. Assisted firmware team in enhancing data path verification and testing methods and the corresponding RTL-FPGA enhancement cycles
  • PCI V2.2 Master/Target IP Core RTL Design, BFM and exhaustive test suite performed UTOPIA Interface, BFM & test cases created to verify the data path between FDMA & DDR SDRAM. Lexra Data Memory: Interface BFM & test cases created to verify the on-chip Dual Port SSRAM & FDMA. HDLC CONTROLLER: Time Division Multiplexing on 8 HDLC Cores, each handling 32 TDM channels.

Education

DIPLOMA IN ASIC PHYSICAL DESIGN -

ATIIT
09.2000

Bachelors in Electronics & Communication Engg (Madurai Kamaraj University) -

Mepco Schlenk Engg College
04.2000

Higher Secondary School - Maths, Physics, Chemistry, Biology

P.A.C.M Hr. Sec. School
Rajapalayam
04-1996

Skills

  • System Verilog, UVM, Perl, TCL, RTL coding, testbench, design for test, timing constraints, report analysis, pre & post silicon verification and debug

Websites

Workauthorization

H1B

Personal Information

Nationality: Indian

Timeline

Sr DFX Engineer

Intel
04.2021 - Current

Sr Staff Engineer

Synaptics
09.2018 - 04.2021

Sr Staff Engineer

Qualcomm
11.2011 - 09.2018

Consultant

Synapse DA (Client: STE, Broadcom, TI)
09.2008 - 11.2011

Technical Leader

NXP
09.2006 - 09.2008

Sr Design Engineer

Texas Instruments
05.2004 - 09.2006

Design Engineer

HCL Technologies
09.2000 - 01.2003

DIPLOMA IN ASIC PHYSICAL DESIGN -

ATIIT

Bachelors in Electronics & Communication Engg (Madurai Kamaraj University) -

Mepco Schlenk Engg College

Higher Secondary School - Maths, Physics, Chemistry, Biology

P.A.C.M Hr. Sec. School

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Balasubramaniam Gopal