Summary
Overview
Work History
Education
Skills
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BASAVARAJ PATTED

San Diego,CA

Summary

Enthusiastic product test, ATE, SLT, ASIC, DFT methodologies, engineering with 15+ years of proven relevant experience & track record in DFT methodologies, test development, characterization, deployment of manufacturing system level testing. Successfully worked across Mobile, Automotive, Telematics (MDM) SoC’s met timeline and cost budget with high quality. Collaborating with cross-functional teams to define product requirements, specifications, and goals. This includes understanding customer needs, market analysis, and setting clear objectives for the product. Experience in Tessent Streaming Scan Network (SSN) architecture designed to streamline the testing of complex System-on-Chip (SoC) designs, Working closely with design teams to develop the product.conducting design reviews, and ensuring the product meets the defined specifications. DFT Tester Pattern generation/conversion, Test Program flow development. Participating in various testing phases to ensure the product’s functionality, reliability, and performance. This includes Design for Testability (DFT) considerations, using tools like Advantest 93K, and performing failure analysis. Overseeing initial production runs to identify and resolve any manufacturing issues. This stage ensures that the production process is efficient and that the product can be manufactured at scale. Supporting the transition from pilot production to full-scale manufacturing. This includes finalizing production processes, training manufacturing staff, and ensuring quality control measures are in place. DPPM reduction. Post-Launch Support: Providing ongoing support after the product is launched, including monitoring performance, addressing any issues that arise, and implementing continuous improvements. Ensure a smooth transition from concept to market, helping to deliver a high-quality product that meets customer expectations

Overview

16
16
years of professional experience

Work History

Staff DFT Engineer

Qualcomm Technologies Inc
05.2016 - Current
  • Collaborated with the testing team to identify and resolve critical ATE failures on a complex SoC design
  • Utilized fault isolation, fault targeting and design analysis techniques to pinpoint root causes, propose effective solutions, and work with the team to implement fixes and environment changes
  • Deploy ATPG scan chain vectors on ATE floor Advantest 93K SMT8 and test them end to end test process
  • Deploy Golden Gate ATPG scan chain vectors on Yushan Handler on Tri-Temp SLT platform for volume ramp up
  • Worked on SLT bring up for tier one Snapdragon Automotive chipsets, advance FinFet technology
  • Identified and resolved Scan DRC's during scan insertion (Mentor Tessent) for a complex design, collaborating with designers to implement fixes in RTL
  • Resolved errors and reviewed warnings during ATPG (stuck-at and atspeed patterns) using TestKompress, ensuring scan chain integrity and preventing potential timing violations in the final design
  • Efficiently inserted scan chains in a complex SoC netlist using Mentor Tessent, achieving 20% test time reduction through optimized stitching
  • Expertise in verifying design at RTL level and gate-level simulation NT & PA simulation
  • Through in-depth analysis of coverage reports and fault simulations, identified critical gaps in stuck-at and transition coverage
  • Strategically inserted wrapper and test points using a combination of automated tools and manual design, achieving 98% stuck-at coverage and 95% transition coverage, respectively
  • Ran no-timing and timing (by annotating SDF’s) simulations to confirm correct functionality of DFT logic
  • Debugged and identified root cause for timing-related X and 0-1 miscompares during simulations of a high-speed SoC design
  • Effectively collaborated with STA team to develop and implement fixes
  • Led the migration of existing scan insertion and ATPG flows from Mentor Graphics to Cadence tools (Genus, Modus) for a complex design
  • Independently updated flow scripts, run directories, and environment settings, ensuring compatibility with the new tools and alignment with established flow standards
  • Reduced migration time by 20%
  • Performed rigorous verification and validation of the migrated flow, achieving a fault coverage of 98% for stuck-at and 95% for atspeed through comprehensive analysis of coverage reports and dft simulations across various testmodes
  • Owning isris/eva ss wrapper, padbanks,ncc cores bring up for ATPG scan chain tracing complete end to end bring up including TOP-LEVEL padbanks, TDF & SAF bring up
  • Owning bring up of PA(Power Aware) & NT (No timing) GLS simulations for IRIS & EVA SS wrapper cores
  • Owning & responsible for generating grayboxes for SoC Kaanapali project
  • Worked on debug of a failing scan chain integrity simulation in GLS timing mode & report fails and required fixes
  • Working on GG (Golden Gate ) SAF ATPG vectors for SLT teams, help reduce the DPPM
  • Work on ATE / SLT Yushan handlers, testers deploy DFT vectors, ATPG & execute the ATE VECTORS
  • Independent contribution on pre-silicon SoC bring up, characterization of power data for various Voltage levels to correlate SLT & ATE, IDDQ data, integrated VI/SVE,I2C,PCIe test contents to test program & debug issues
  • Root caused RMAs across multiple SoCs and helped to improve ATE test coverage.

Post silicon support

Enaphase Enegry Inc
08.2015 - 11.2016
  • Post silicon support to ensure successful bring up and enhance yield learning
  • ATPG patterns verification with gate level simulation
  • Scan/Jtag/boundary scan insertion and ATPG pattern generation
  • Test coverage and test cost reduction analysis
  • Implementation and verification of DFT architecture and features
  • Work in close collaboration with frontend, verification, backend and test engineering teams.

Contract through Infinite Solutions Inc

QUALCOMM Technologies Inc
11.2011 - 08.2015
  • Involved in bringing up MSM8974, MSM8992, MSM8996 mobile chipsets, involved in making daily builds to bisect the issues observed identified SW stability bugs and supported customer RMA debug and root cause
  • Developed Test programs in QSPR, enhancement & additions of new test nodes to test tree
  • Responsible for Burn-In Test Program development and content integration on Self Heat tester to meet Intel DPM goals
  • Debugged fails and developed solutions to meet PHIs in the manufacturing flow
  • Continuous improvement of PHI parameters for maximum yield.

SAMSUNG India Pvt Ltd
12.2008 - 11.2011
  • Involved in HW/SW bring up, debugged pre-silicon SoC issues
  • Worked on ATE, deployed DFT vectors, achieved reduce the DPPM, by debug and fixing the failing vectors
  • Hands-on experience of using Oscilloscope and DMM in a lab setup.

Education

Skills

  • ATPG / DFT tools: Tessent, System Verilog Synopsys SMS flow and Shell flow
  • Mentor Tessent, Data Analyses: Optimal Plus(O), DataPower, Extenso, Advantest 93K Smart test 8
  • Tools & OS: QxDM, QPST, Jira, JTAGCratos,Oscilloscope, Android, Perforce, GIT/GerritsEmbedded Linux,UNIX,
  • Excellent coding experience of PERL, Python, TCL, Knowledge of C,C programming

Accomplishments

Achieved several Qualstar awards, best execution, Samsung – Best employee of the month & Best employee of the Year.

Home

(858) 901-2243

Timeline

Staff DFT Engineer

Qualcomm Technologies Inc
05.2016 - Current

Post silicon support

Enaphase Enegry Inc
08.2015 - 11.2016

Contract through Infinite Solutions Inc

QUALCOMM Technologies Inc
11.2011 - 08.2015

SAMSUNG India Pvt Ltd
12.2008 - 11.2011

BASAVARAJ PATTED