Binh Dang

Hardworking and self-motivated individual with strong passionate about hardware infrastructure that run the worlds.

• For the next decade, I wish to be able to grow and excel in VLSI field as a Hardware Design Engineer and contribute to the world technology with my knowledge and passion.
• In the long term, I wish to be a lecturer equipped with industrial experience to guide the next generation in the respected field.

High-speed custom FPGA-based SPI-to-ETH bridge for accelerating real-time Electrical Impedance Tomography systems

Sep, 2023 - Mar, 2024

• Developing efficient micro-architecture for SPI Controller interface for high-throughput transmission
• Developing the IEEE802.3 100Mbps Ethernet MAC with MII interface (Clause 22) to establish a connection with 100Mbps PHY.
• Developing a bridge-like micro-architecture that can efficiently transfer data back and forth between the SPI Controller interface and 10/100Mbps MII Peripheral interface to support real-time systems
• Implementation device: Xilinx Arty A7-100T FPGA

The novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA 

Jun, 2022 - Oct, 2022

• Be responsible for developing the CAM microarchitecture to support ternary values.
• Developed a customized read/write algorithm of the microarchitecture for resource efficiency
• Documented the microarchitecture and constructed the paper using LaTEX
• Tools used: Microsoft Visio, Intel Quartus Prime, Questa Modelsim
• Implementation device: Intel Altera DE10 Standard (Cyclone V FPGA)
• Publication: N. Trinh, M. Bui, B. Dang, and L. Tran, “A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA,” Ain Shams Eng. J., p. 102478, Sep. 2023, doi: 10.1016/j.asej.2023.102478.

Parameterized SDRAM-based Content-Addressable Memory on FPGA 

Oct, 2021 - May, 2022

• Conducted research and gathered information from multiple technical papers
• Came up with the System Architecture that is compatible with embedded SDRAM on FPGA board. Sketch and develop an effective algorithm for each functional block.
• Used Verilog-HDL to design functional blocks using conventional control-path, data-path, and pipeline techniques.
• Developed Intel Avalon Memory-Mapped controller/peripherals interface for controlling read/write operation to/from on-chip SDRAM Controller Subsystem and interconnects with the Intel HPS-to-FPGA bridge
• Built Qsys system and worked with Linux and wrote C programs to transfer data to FPGA fabric. Reserved 512MB in memory for boot region and memory region
• Documented the microarchitecture and constructed the paper using LaTEX
• Tools used: Microsoft Visio, Intel Quartus Prime, Questa Modelsim
• Implementation device: Intel Altera DE0-Nano-SoC (Cyclone V FPGA)
• Publication: B. Dang, M. Bui, N. T. V. Dang, and L. Tran, “Parameterized SDRAM-based content-addressable memory on field programmable gate array,” Indones. J. Electr. Eng. Comput. Sci., vol. 31, no. 2, Art. no. 2, Aug. 2023, doi: 10.11591/ijeecs.v31.i2.pp669-680.

Cadence Training

• Basic Static Timing Analysis v2.0 Exam Certificate

Qualcomm Academy

• Fundamentals of Cellular Communication and 5G
• 5G Primer

Udemy

• SystemVerilog Assertion & Functional Coverage FROM SCRATCH

Coursera

• Computer Architecture
• Build a Modern Computer from First Principles: From Nand to Tetris (Project-Centered Course)
• Digital Systems: From Logic Gates to Processors
• FPGA Design for Embedded Systems Specialization