BHARATH CHITTIMILLA

1. I2C Master Core IP – Lattice – Sub-system level

Duration: 5 months (Mar 2022 – Aug 2022)

Team size: 01

Environment: UVM and System Verilog

Role

• Understanding I2C Master Core IP Protocol Design Specification and Its Features.
• Test case development for all the spec features.
• Developed all TB components from scratch.
• Debugging and fixing test failures, and filing RTL bugs.

2. Ethernet MAC – IP level.

Duration: 10 months (Aug 2022 - July 2023)

Team size: 5

Environment: UVM and SystemVerilog, Role:

• Verification and analysis of Ethernet VIP.
• Implemented checks. MAC layer monitor functionality with protocol checks.
• added the logic to capture and process the packet in standard order, in the scoreboard component.
• Compared the data of packets from multiple monitors.
• Debugged and fixed test failures.

1. AXI -IP level

Duration: 5 months (Aug 2021 - Jan 2022) Environment: UVM and System Verilog Role:

• Understanding AXI protocol designs, specifications, and their features.
• Developed UVM TB components.

Test case development and verification of the environment with multiple test cases.

• Debugging and fixing test failure.

2. APB – IP level

Duration: 5 months (March 2021 - August 2021)

Environment: UVM and SystemVerilog. Role

• APB Protocol Specification Study. protocol
• Implemented a basic UVM environment for a single master for the slave DUT.
• Implemented basic FSM-based write and read transactions in the master driver component.
• Debugging and fixing test failures.

3.Designed ALUtest-bench in UVM.

Duration: 2 months (Jan 2021 - March 2021)

Environment: UVM and SystemVerilog.

Role

• The goal was to develop a test environment to test the APB protocol of a slave device.
• Developed a complete test bench to test the ALU DUT.