Bhasker Vanamali

Part of Device and Development Group (DDG), responsible for HuB part of the chipsets. Involved in Chassis upbringing.

NVL - Intel 1.8A node. 2.4 GHz / 2.4 Mill GC partition. RTL - GDS implementation.

• Complexity - 6 Power Domains. 5 SubFC interfaces. Logic bound - CTS recipe. Clock is DLVR in MMMC.
• Achievements - 2.4GHz clock timing closure at 0.5V with high logic depths. Hier UPF.
• This partition work required a lot of engagement with RTL/PnP to come up with optimal solutions/Arch fixes for backend implementation.
• Cooperation with Power and Lib team to provide better libraries to meet spec. Daily conversations with SNPS to get FC to bring out the best PPA.

MTL - TSMC 7nm. 2.0 GHz / 2.0 Mill GC. RTL - GDS implementation.

• Complexity - 4 Power Domains. 5 SubFC interfaces. High logic depth. Congestion due to Big HIPs - VA - Interface. 2nd PG hook up for AON cells due to congestion. CLock is DLVR in MMMC.
• Achievements - Timing closure with relatively low ULVT%. Faster turn around in B0 stepping.
• Backend had to do multiple trials in terms of FP and logic placement due to congestion.
• Supported five different partitions during this project.

Additional responsibilities within DDG

• Created an internal document on best practices for Synthesis. it is referenced across multiple teams.
• Undertook methodology work for IR-aware STA in CDNS partitions. It is now part of CDNS flow.
• IR ownership for Static / Dynamic / EM within my sub system - 12 partitions. Provide feedback based on violations and respective locations.

MGR - Intel 10nm. 2.8 GHz / 1.4 Mill GC. RTL - GDS implementation

• Complexity - Crosstalk/Noise arising out of logic placement. Constraint tune up w.r.t repeater. Multiple partition handling
• Achievement - quick turnaround on 5 complex partition within this project
• At any given time, i was responsible for 3 partitions. I have handled a total of 15 partitions during the course of this project. Most of the partition were Fabric partition with relatively medium timing complexity but required specific logic placement. MSCTS and fine tuning clock was considerable part of the work.

LBG - Intel 14nm. 1.6 GHz / 1 Mill gc. Server PCH. RTL - GDS implementation.

• Complexity - Timing, Leakage.
• Achievements - Leadership role, faster turnaround on closure.
• I have owned 2 complex partitions at any given time. At the same time I was leading 3 Juniors handling 2 blocks each.
• I bought in my previous experience with PCH and helped closing the block with minimal leakage concerns.

Camera Chip - Intel. 22nm / 8Mill gc. RTL- GDS implementation. Project Discontinued

• I was the overall PD lead for this project with 8 engineers under me. This was a small chip ~8mill gatecount, 60% were PLLs, Fuse. the rest of the logic divided into 3 sub partition.

As a lead, my work involved in ...

• Porting flow from a different project.
• logic partitioning - conversations with Front End Team
• Clock creation / routing. CDC.
• rtl list generation with from Front end for backend consumption.
• Defining constraints at partition level.

PCH - Intel Malaysia. 22-14nm. 1.5GHz. 1 Mill - 500k GC. RTL - GDS implementation.

• Achievements - Leakage
• Over a course of 6 years, I have worked exclusively with Intel Malaysia in their PCH projects. Worked on Sunrise point (H and LP), Canon Lake (H & LP), Kaby Lake (H and LP), Ice Lake (H), Lewisberg (H, Server)
• Executed multiple Functional Eco spins for all these projects.
• At any given time i owned 2 upto a max of 5 partitions.
• I have been a lead in all the projects. My team size ranged from 3 to 17 members. Icelake being the largest with 22 partition responsibility.