Bhavna Bakhru

• Led a team in developing and releasing DEB and RPM packages through an automated build and release process.
• Enhanced software quality through the integration of security checks and automated testing into the pipeline.
• Engaged in contributing to an Open Source Linux Project on GitHub.
• Implemented effective software engineering practices to optimize development cycle time while ensuring high standards of quality.
• Coordinated stakeholder collaboration for successful product delivery across multiple departments.
• Designed innovative solutions for challenging business problems using modern technologies.

• Managed a team of engineers and drove strategic initiatives, optimizing processes, and delivering high-quality products within schedule and budget.
• Collaborated with cross-functional teams to design and develop the Intel Platform Resource Access API, a RESTful API to discover and monitor HS/SW resources on client platforms.
• Mentored junior engineers on developing reliable products that meet customer requirements.

• Managed TypeC program, collaborating seamlessly with architecture, design, and cross-functional teams for successful project delivery.
• Implemented latest features and delivered first SOC agnostic IP with high quality.
• Developed new and enhanced validation methodologies at Centre of Excellence to drive engineering efficiency and ensure faster turnaround time for project deadlines.
• Led multiple task forces and dungeons, ensuring adherence to quality standards.
• Managed a team of 10 engineers, delegating tasks and monitoring progress to ensure quality control standards.

• Championed design validation activities involving feature scoping, risk management, strategy, and planning. Led an initiative to enhance methodology and implement a shift-left approach for Netlist build of an IP. Successfully reduced the build time from weeks to a single day.
• Led and directed a team responsible for developing test strategies, plans, and schedules for post-silicon validation. Successfully drove implementation of these strategies to completion.
• Reviewed BDV, MRC, and SVE test plans for Design/MRC-specific ECOs. Gained hands-on lab experience with measurement and debug tools in validating critical sightings.
• Created and optimized essential circuit components for DDR MIG module while ensuring compliance with specifications and upholding top-notch quality standards.
• Operated mixed signal validation and included all necessary tests to validate the ANA-DIG interface following Jedec protocol.
• Successfully contributed to the creation of a dedicated BMOD team in MIG by spearheading the adoption of this valuable skillset.

Successfully conducted SIM2SIL validation and correlation for the analog front end and clocking sections, ensuring accurate simulation-to-silicon transition.

Demonstrated strong ability in responsibilities including circuit characterization, simulation, validation, lab data collection, presentation, and reviews.

Transitioned into full-time role as part of Hard IP Memory team, overseeing Circuit Design, Quality, Schematic development, simulation and ensuring quality throughout Technical Readiness phase to Production.

Collaborated with RTL/DFX/SOC teams in delivering high-quality behavioral models to customers.