Biplob Daas
Portland,OR
Summary
Skilled engineering manager builds and motivates high-performing engineering team. Over 12 years of experience in Intel working with Client/Server products. Committed to rapidly and efficiently completing projects by leveraging team-based frameworks to best leverage available engineering talent.
Overview
13
13
years of professional experience
Work History
Sr. Product Validation Engineering Manager
Intel
01.2019 - Current
- Leading a dynamic team of over 15 engineers to conduct rigorous product platform validation (PPV) system debugging across a range of products including MTL, TGL, ADL, RPL, etc
- Proactively addressing silicon and design-related issues prior to customer delivery and DPM impact
- Oversight includes validation across IA compute, Windows, Graphics, SOC, and power management within the system platform, with active collaboration across diverse organizational units within Intel (STTD, iVE, SIV, CCG, PNG, BGA, etc.) across various geographical locations.
Analog Product Development Technical Lead
Intel
01.2014 - 01.2019
- Leading a 25+ member team within the Client Analog (AST) organization, I drive resolution of technical issues pertaining to Analog components (PLLs, IOs, DDR, PTH) across diverse product portfolios (TGL, MTL)
- Responsibilities encompass Pre-Si validation, post-Si test development, Si validation, Package validation, stress validation, and other Intel process-implemented sockets for End-2-End execution
- Direct oversight includes High-speed IO, Wideband IO, DDR, Clock/PLL, and Power-Thermal disciplines, ensuring product performance meets design expectations and IP test quality standards
- Extensively collaborating across US and international sites (PG, BN, IDC) and product segments (Client, SOC, Server) within MPE manufacturing organization
Sr. Product Development Engineer
Intel
01.2012 - 01.2014
- In this role, I focus on enhancing efficiency across sort, class, and burn-in testing by addressing SIU/TIU hardware disparities on test chips
- Additionally, I spearhead module development and debugging to meet product requirements, encompassing various components such as PLLs, DDR, IDV, PCIe, SIO, NIO, GPIO, Serdes, DFG, ARRAY, FUNC, and ATOM
- This involves devising test methodologies from RTL design to silicon implementation, alongside essential debug processes to optimize design, defect, and test margins.
Education
PhD - Electrical Engineering
University of South Carolina
01.2012
Skills
- Semiconductor Technology
- Circuit Design
- CAD Tools
- Process Technology
- Failure Analysis
- Test and Validation
- Quality Assurance
- Embedded Systems
- Thermal and Power Management
- Communication
- Collaboration
- Negotiation
- Conflict Resolution
- Customer Focus
Personal Information
Title: Sr. Product Validation Engineering Manager
Key experience
- Over 12 years of leadership experience in leading a team for Intel Client product validation for several generation with E2E execution. Starting from NPI into MP ramp, provided enhanced quality with reduced test time cost by implementing manufacturing test methodology for Client products; refine, revise and overhaul test and manufacturing flows; collaborate with test engineering to specify and develop new testers and infrastructure that meet production requirement targets.
- Led a team of 25+ professionals within Intel Client Product organization, providing delivery of multiple Intel products (MTL,ARL,RPL,LNL,TGL etc.) collaborating with architecture, hardware, software and other product engineering teams to improve manufacturing tests, production yields and cycle times. Drove debug effort both in ATE and System platform across functional groups to successful closure and towards continued yield/DPM/margin improvement.
- Experience in setting clear goals, maintaining accountability, and implementing differentiated performance management systems to drive team results and individual growth towards aggressive deliverable for industry growth.
- Technical hands-on experience on debugging System issue (GPU, GFX Driver, GFX bench, GT,SOC, CPU, PM, PKGC etc.) as well as ATE issue ( DDR, CLK, PCIE, USB, TCSS, SCAN, ARRAY, DTS, DLVR etc.)
- Proficient in TP development/debug/analysis at both ATE and System platform, addressing design optimization features and hardware in Pre and post-Si phases.
- Skilled in SIU,TIU, RVP, MB design to accommodate design changes for effective data generation across various process nodes with optimized cost and greater coverage with signal integrity and high-speed interconnect.
- Possess 2+ year of experience as a TD process Integration engineer for Technology for Intel 14nm & 10nm process development and yield performances.
Timeline
Sr. Product Validation Engineering Manager
Intel
01.2019 - Current
Analog Product Development Technical Lead
Intel
01.2014 - 01.2019
Sr. Product Development Engineer
Intel
01.2012 - 01.2014
PhD - Electrical Engineering
University of South Carolina
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