Brian Bui

The tools that I am familiar are Cadence XL for layout, and Mentor Calibre for DRC/LVS verification. Some of the processes that I have worked on and experience while at ISEELAYOUT is TSMC 180nm, 28nm DNW, TSMC 55nm DNW, ln08lpp, ln14lpp, and little bit of knowledge of 5nm node. I have worked on many cells and block at I SEE LAYOUT but some cells/blocks have included a bitdec, opamp, levshft, and a bandgap. For all the different processes that I have worked on I would do the initial placements of the transistors, and once the placements were done, I would then ask the circuit designers review them before I would start the cell or block level integration.