CHETANDEEP SINGH
LEANDER
Summary
Emulation technologist driving pre-silicon verification through innovative Shift Left methodologies. Developed and deployed hardware testbench architectures to optimize throughput across emulation workloads. Increased emulation footprint tenfold in key accounts by leading competitive displacement initiatives.
Overview
19
19
years of professional experience
Work History
Principal Emulation Engineer
Mentor Graphics Inc. (Now Siemens EDA)
Austin
04.2014 - Current
- Develop hardware testbench architecture and infrastructure (Systemc/C/SV/UVM) to maximize throughput across emulation and prototyping workloads.
- Build emulation/prototyping models for Mentor's HW technologies and Bring-up SoCs (CPU/GPU/Networking) end-to-end along with Protocol Solutions (ICE and Virtual) by debugging non-functional cases, and improve QoR to increase productivity.
- Develop Shift-Left emulation methodologies to solve customer issues and increase tool adoption. e.g. Developed DFT Acceleration Flow for running serial test patterns on emulation.
- Built Emulation Metric Collection and analytics toolset using Python/Dash to track compile/runtime performance data-points across accounts.
Member Consulting Staff
Mentor Graphics India
Noida
01.2010 - 04.2014
- Part of R&D group responsible for Methodology and Emulation Solution Development and Deployment.
- End to End Bring up (Compile/Runtime/Debug) for Worldwide Customer SoCs on Mentor's HW platform to drive emulation adoption.
- Developed Cache Based Memory models for HW-SW Hybrid Access Solutions using Locality of Reference.
- Custom Transactor development in Systemc/UVM using DPI Standards. e.g. TLM2.0 based Acceleration Flow for SystemC fast models.
- Developed Virtual PCIe Root-Complex Solution prototype using Qemu Hypervisor as ICE replacement methodology.
Senior Member Technical Staff
Interra Systems
Noida/Bangalore
08.2007 - 12.2009
- Developed of H.264 decoder Verification IP in SystemVerilog AVM.
Education
Bachelor of Engineering - Electronics and Communications Engineering
Thapar University
Patiala, India07-2007
Skills
- SV/Verilog/UVM simulation acceleration
- SystemC/C/C
- Transactors
- RTL
- BFMs
- In-Circuit Emulation (ICE)
- PCIe
- DDR4/LPDDR5
- AXI
- MIPI/CSI
- Power Aware UPF
- Python/TCL
- Veloce Emulation
- Emulation offload with Veloce Prototyping
Websites
Additional Information - Greencard Holder
True
Honor Awards
- Worldwide Emulation Applications Engineer of the Year 2020/21, 2015/16
- Technical Excellence Awards 2016/18/19
Timeline
Principal Emulation Engineer
Mentor Graphics Inc. (Now Siemens EDA)
04.2014 - Current
Member Consulting Staff
Mentor Graphics India
01.2010 - 04.2014
Senior Member Technical Staff
Interra Systems
08.2007 - 12.2009
Bachelor of Engineering - Electronics and Communications Engineering
Thapar University