Summary
Overview
Work History
Education
Skills
Timeline

ChienHun Matt Tung

Cupertino,CA

Summary

Solid experience with 15 years of semiconductor technology development and supplier manufacturing on mixed signal communication and power analog products. Extensive skills in supplier quality matrix, IQC/OQC and Foundry/OSAT quality management.

Overview

17
17
years of professional experience

Work History

Technical Leader SQE (contractor)

Cisco Inc.
02.2024 - 12.2024
  • To handle ASIC network accelerator NPI reject and RMA and customer’s test log review, fault isolation, test plan, test correlation and degradation analysis, 2.5D package die reliability analysis and FA/8D.
  • Achievement: 7~5nm ASIC/HBM network co-packaged InFO interconnect, data link analysis, FA/8D.

Sr. Staff Foundry Engineer

Renesas Electronics
02.2022 - 06.2023
  • RF FEM, FinFET timing clock tape out and process development in foundries, wafer process flow SPC, WAT, WS/FT analysis and to drive BKM improvement on product reliability weakness, customer needs.
  • Automotive HWs reject RMA failure analysis, RCCA and to drive supplier improvement & generate 8D.
  • Achievement: Beamforming, mmWave, LNA, Switch, PMIC fab process optimization, golden route.

Staff Supplier Quality Engineer

Renesas Electronics/Dialog Semi
01.2021 - 01.2022
  • VRs, PMIC product rejects and RMA test log diagnosis, wafer, packaged die degradation analysis; ppm failure tracking, die history tracking, WAT & CP/FT analysis, SOA and process improvement for yield.
  • Automotive chips reject fault isolation, FA, RCCA and 8D in foundry/OSAT and host CCB, MRB.
  • Achievement: 0.13/0.18um PMIC product process optimization for SOA, IO/ESD and yield ramp up.

Sr. Staff Product Engineer/Team Leader

Samsung Semiconductor
10.2017 - 10.2020
  • Lead taskforce to bring up GPU, ASIC NPI, design mask OPC, reliability test and create process flow.
  • Liaison across process integration and fab process teams to achieve devices target and reliability; to implement test and burn in plan, set up GDPW SBL/SYL, wafer DVS test and yield improvement.
  • Present weekly status and product test yield/DD roadmap to executives, managers and customers.
  • Timely monitor fab inline data, CP/FT data analysis correlation bin report and generate CIP to customers.
  • Achievement: 14nm GPU failure pathfinding in Gate, S/D, CO, Mx loop; achieve yield and reliability.

Technology Access Engineer Lead/Foundry Manager

Intel Inc.
04.2013 - 08.2017
  • Wireless & network connectivity, photonic IC wafer enabled manufacturing, wafer sort yield analysis, and design process technology co-optimization; DVT, PVT silicon debug and process failure path finding.
  • Wafer and packaged die reliability qualification plan, quality matrix and qualification problem solving.
  • Achievement: 28nm HPL, 16nm HPC+ FinFETs SRAM, IP process technology & design co-optimization; finding for improving reliability weakness and low yield; to achieve device performance and fab KPI.

Sr. Staff Technology Development Engineer

Cypress Semiconductor
12.2010 - 04.2013
  • Processor, CIS, SRAM, memory controller wafer fabrication development, device process skew DOE and Si debug, wafer assembly manufacturing yield analysis and drive CMs for yield ppm improvement.
  • Product characterization DVT, PVT, wafer & IC reliability test plan and implement solution on process.
  • Achievement: 28nm HPM mixed signal logic, SRAM and NVM IP development in tsmc and UMC.

Manufacturing Engineer

NVIDIA Inc.
12.2009 - 12.2010
  • Tegra Processor and GPU final test and system level test manufacturing, HW/SW bring up and yield improvement; improve test efficiency, waste reduction, HW production operation flow set up.

Process Integration Engineer/Foundry Interface

Texas Instruments
09.2007 - 12.2009
  • BCD HV process technology integration and transfer to fab partner and enable production ramp up.
  • Mixed signal baseband and wireless communication ICs tape out DRC clearance on violation, device model and insufficient silicon improvement, wafer process skew design and reliability robustness BKM.
  • Achievement: 65nm cellular baseband modem, WiLink production ramp up and met business goal.
  • 0.35um BCD process technology transfer and generate backend bump to improve characteristics.

Education

Master of Sc - Electrical Engineering

UNIVERSITY OF SOUTHERN CALIFORNIA

Bachelor of Sc - Materials Science Engineering

UNIVERSITY OF SOUTHERN CALIFORNIA

Skills

  • Extensive use of MS Word, Excel, Power Point, Project, Smart Sheet, PLM, JIRA, Confluence
  • SKILL: BD/Pin Assignments, Layout design, ISO9001, AECQ-100, AS9145, FMEA, SPC, 6 Sig, GRR
  • TOOL: Allegro, Virtuoso, OrCAD, SQL, VLOOKUP, LabView, JMP, Tableau, Exensio, ERP, SAP

Timeline

Technical Leader SQE (contractor) - Cisco Inc.
02.2024 - 12.2024
Sr. Staff Foundry Engineer - Renesas Electronics
02.2022 - 06.2023
Staff Supplier Quality Engineer - Renesas Electronics/Dialog Semi
01.2021 - 01.2022
Sr. Staff Product Engineer/Team Leader - Samsung Semiconductor
10.2017 - 10.2020
Technology Access Engineer Lead/Foundry Manager - Intel Inc.
04.2013 - 08.2017
Sr. Staff Technology Development Engineer - Cypress Semiconductor
12.2010 - 04.2013
Manufacturing Engineer - NVIDIA Inc.
12.2009 - 12.2010
Process Integration Engineer/Foundry Interface - Texas Instruments
09.2007 - 12.2009
UNIVERSITY OF SOUTHERN CALIFORNIA - Bachelor of Sc, Materials Science Engineering
UNIVERSITY OF SOUTHERN CALIFORNIA - Master of Sc, Electrical Engineering

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