Hi, I’m
Chun-Hung (Alex) KO
Glendale,AZ
Summary
- 15+ years working experience in semiconductor industry, and all stayed in advance technology nodes, which are N28/N10/N7/N6/N5/N4 in Fab Qualification & Reliability (2013~now) and N40/N20 in Research & Development process integration( 2006~2013).
- In Fab Q&R: led and managed cross-fab technology transfer, accomplished technology qualification, customers handling, includes RMA(return materiel authorization)/8D report/reliability assessment, reliability DPPM reduction.
- In R&D process integration: Adept at driving continuous improvement actions , managing process engineering projects, device boost/yield ramp-up/reliability marginality.
- Led N6/N7 Q&R technology qualification GDS team(3DIC/RF/HVMOS), familiar with layout design, design rule check and new tape-out procedures.
Overview
22
years of professional experience
Work History
TMSCPhoenix, AZ
Q&R Priciple Engineer(N4/N5)
11.2022 - Current
Job overview
- Lead six Q&R automation projects. Use Uipath to improve working efficiency(30%~70%)
- Supervise N4 Technology Transferred from Taiwan mother Fab to AZ Fab
TSMC, Taiwan(Tainan-site)
Q&R Priciple Engineer(N4/N5)
01.2022 - 10.2022
Job overview
- Guided Mother Fab for WAT layout enhancement, and fan-out to N5/N4/N3.
- Collaborated with Mother Fab for N4 process qaulification(TDDB/SM/EM/Vbd/PID)
TSMC, Taiwan(TaiChung-site)
Q&R Priciple Engineer(N6/N7/N10/N22/N28)
06.2013 - 12.2021
Job overview
- Led and Managed N6/N7 tech qual NTO(GDS preparation, Design rule check)
- Customer handle, includes Intel/Apple/TI.(reliability assessement, RMA and 8D report)
- Initiated 1st Q&R reliability WAT testline and implemented from N28 to leading-edge Tech
TSMC, Taiwan(HsinChu-site)
R&D Senior Engineer(N20/N40)
11.2006 - 06.2013
Job overview
- Performed and optimized process integration(CESL/DMY_PO&IL/HK/MG/IMP)
- Analyzed and determined root cause of process and yield issues
- Accomplished N20 1st customer NTO(Orcle) pi-run successfully
- In charge of N40 SRAM production qualification (D303/DP600)
Industrial Technology Research Institute, Taiwan
Optics Engineer
10.2002 - 10.2006
Job overview
- Developed optics measurement equipment (10 USA/Taiwan patents; 5 published papers)
- Project leader of Optics Critical Dimension (OCD) measurement(co-work with TSMC)
Education
National Chaio Tung UniversityHsinChu, Taiwan
Master of Science from Electro-Optical Engineering
06-2002
National Chiao Tung UniversityHsin-Chu, Taiwan
Bachelor of Science from Electro-Physics
06-2000
Skills
- Robotics Engineering
- Nanotechnology
- System Design
- Root Cause Analysis
Custom
1. 2014’11’04 US patent 8,877,614 “Spacer for semiconductor structure contact”
2. 2014’09’16 US patent 8,835,242 “Semiconductor structure and method”
3. 2014’05’27 US patent 8,735,258 “Integrated circuit resistor fabrication with dummy gate removal”
Languages
English
Professional
Timeline
Q&R Priciple Engineer(N4/N5)
TMSC
11.2022 - Current
Q&R Priciple Engineer(N4/N5)
TSMC
01.2022 - 10.2022
Q&R Priciple Engineer(N6/N7/N10/N22/N28)
TSMC
06.2013 - 12.2021
R&D Senior Engineer(N20/N40)
TSMC
11.2006 - 06.2013
Optics Engineer
Industrial Technology Research Institute
10.2002 - 10.2006
National Chaio Tung University
Master of Science from Electro-Optical Engineering
National Chiao Tung University
Bachelor of Science from Electro-Physics