Corrina Mellinger

• Responsible for multi-hierarchical, physical layout, clean up.
• Expert in design rule violations and debug on CMOS processes.
• Established strong relationships with cross-site teams, to deliver partitions on time, to targeted deadlines.
• Managed multiple projects simultaneously, meeting tight deadlines without compromising on quality.
• Expert user in Synopsis, Fusion Compiler.
• Mentored junior designers, sharing industry knowledge and best practices to elevate team performance.
• Performed early analysis on partition designs, to support high quality layout, for final clean up.
• Managed layout tasks for our Mask Design team; assigning tasks, correspondence between Engineering and management and updating Excel spreadsheets accordingly.
• Generated timing and extraction reports and analyzing the results for changes and edits to the layout

Contractor Mask Designer, responsible for layout of integrated circuits.

• Worked with in house, layout tools to draw and design simple to complex gates.
• Worked closely with the Design Engineers to ensure high quality layout, based on their schematics.
• LVS/DRC debug, fixes and drive to clean layout

Contractor Mask Designer, responsible for layout of integrated circuits with HP/Intel co project. Fet level layout, design rules flows and fixes, back end verification of clean designs.