DAKSHA VIJAYAKUMAR
San Jose
Summary
Design Verification Engineer with three years of experience in SystemVerilog, UVM, scripting, and C++ (core, OOP, reference modeling for scoreboards). Demonstrated success in developing and executing block- and chip-level verification plans, achieving 97% overall coverage. Skilled in regression triage, debugging complex hardware/software interactions, and enhancing verification infrastructure for advanced ASIC projects. Effective collaborator in distributed team environments, and experienced with AI-powered tools such as Copilot and Cursor, to accelerate verification cycles.
Overview
3
3
years of professional experience
Work History
ASIC Engineer 3
Juniper Networks
Sunnyvale
01.2023 - 09.2025
- Developed and executed block-level verification plans for cache memory and ingress result processor blocks, achieving 99% functional coverage for key packet processing logic.
- Developed and executed feature tests through collaboration with cross-functional teams and analysis of architectural specifications, guaranteeing comprehensive and timely test plan completion.
- Partnered with RTL designers to debug and resolve functional issues through and beyond RTL freeze, accelerating bug closure and design sign-off, enabling 95% code coverage.
- Executed incremental feature updates in C++ co-sim models, optimizing legacy features with newly defined macros, employing DPI calls to address functionality, accelerating feature verification process by 40% while enhancing design accuracy
- Automated porting of legacy test-bench components with Python scripts, reducing bring-up time by 30%.
- Performed chip-level and subsystem-level debug to isolate and resolve failures at the block level, supporting root-cause analysis.
- Assisted software teams by verifying bug resolutions with their configurations, ensuring the timely closure of legacy issues.
- Maintained and improved UVM-based test-bench architecture for supported blocks, emphasizing clean, reusable, and well-documented code.
Logic Design and Validation Intern
Intel Corporation
San Jose
08.2022 - 12.2022
- Automated retrieval and conversion of GPIO pin data from .csv to SystemVerilog structures, streamlining UVM sequence generation for test case development and enabling robust assertions on Test Chip GPIO data reducing the manual test setup time by 25%.
- Debugged regression failures for hard IP blocks within a full chip verification environment, assisting block owners for faster bug resolution and improved deliverable quality.
ASIC Hardware Engineer Intern
Palo Alto Networks
San Jose
05.2022 - 08.2022
- Developed a performance rate checker to monitor packet traffic and measure latency, reporting transaction errors by analyzing bus interface signals between network modules.
- Built high-traffic, packet size variant stimulus sequence, enhancing corner-case verification robustness by 15%.
- Gained practical exposure to Jenkins CI workflows and CS register programming for hardware validation.
Education
Master of Science - Electrical Engineering
12-2022
Bachelor of Engineering - Electronics And Communications Engineering
07-2018
Skills
- SystemVerilog and UVM methodology
- Python and Perl scripting
- C co-simulation
- Debugging expertise
- Verification tools familiarity
- FPGA prototyping
- Collaboration and problem solving
- Clear communication and documentation
- AI tools exposure
Academic Projects
Neural Network Engine with NoC : Designed and verified a pipelined multi-layer neural engine (4096 neurons, sigmoid activation, 300 MHz) with custom NoC integration and high-throughput arbitration; performed UVM-based verification, synthesis, timing, and optimization with Synopsys tools.
Developed an FPA adder and RTL-verified a 4-stage, 16-bit IEEE 754 FPA; synthesized and emulated on FPGA with user input via keypad.
Timeline
ASIC Engineer 3 - Juniper Networks
01.2023 - 09.2025
Logic Design and Validation Intern - Intel Corporation
08.2022 - 12.2022
ASIC Hardware Engineer Intern - Palo Alto Networks
05.2022 - 08.2022
SAN JOSE STATE UNIVERSITY - Master of Science, Electrical Engineering
VISVESVARAYA TECHNOLOGICAL UNIVERSITY - Bachelor of Engineering, Electronics And Communications Engineering