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David Pastuch
Senior FPGA Engineer
Rochester,NY
Summary
Experienced with FPGA design and integration in custom SDR applications. Primarily utilizes VHDL, Verilog and C to create embedded designs for Zynq 7000-series, MPSoC, and RFSoC devices according to customer requirements. Strong analytic skills and excellent communicator.
Overview
7
7
years of professional experience
1
1
Language
Work History
Senior FPGA Design Engineer
Vanteon
05.2021 - Current
- Created FPGA designs in VHDL using Xilinx Vivado targeting Zynq 7000-series SoCs, MPSoCs, and RFSoCs for applications such as SDRs
- Debugged designs using Vivado Integrated Logic Analyzers, external logic analyzers, and oscilloscopes
- Aided in debug of SDRs using spectrum analyzers and signal generators
- Wrote C code for both baremetal and embedded Linux platforms running on Xilinx SoCs that interfaced with both Xilinx and custom IP cores
- Customized an Analog Devices transceiver interface IP core to optimize resource utilization for lower resource count parts
- Simulated designs using both VHDL and SystemVerilog testbenches, including designs with Xilinx AXI Verification IP blocks
- Created project scripts to cleanly set up and build Vivado projects that use the GUI project flow
- Helped configure the Xilinx RF Data Converter for customer applications requiring large amounts of instantaneous bandwidth (1GHz) centered at arbitrary points over a wide spectrum (~3GHz)
- Brought up Xilinx PS PCIe on an MPSoC and optimized a custom DMA core to support high throughputs (~4Gbps)
- Aided in development of multi-channel synchronized SDR designs
- Helped design a Zigbee mesh network to act as a BACnet tunnel
Engineering Intern
Vanteon
05.2020 - 08.2020
- Helped develop IoT demo showcasing a star network of temperature sensing endpoints with data collected by a single SDR utilizing a channelizer DSP core
- Researched BLE 5.1 for feasibility of creating a BLE sniffer using Texas Instruments launchpad development kits
- Worked on Petalinux build process for custom SDR
Research Lab Intern
Rochester Institute of Technology, RIT
05.2019 - 08.2019
- Aided in design of a low-power multiply-accumulate unit written in VHDL using posits instead of fixed point arithmetic
- Created Python scripts to generate feedforward neural networks using custom IP cores as nodes
Engineering Intern
Techwell Consulting
05.2018 - 08.2018
- Performed debug of RMA units using test fixtures, multimeters, and oscilloscopes
- Repaired RMA units by replacing damaged surface mount components as small as 0402 resistors and capacitors by hand, as well as creating blue-wire mods for designs with defects
Education
Master of Science - Computer Engineering
Rochester Institute of Technology
Rochester, NY05-2021
Bachelor of Science - Computer Engineering
Rochester Institute of Technology
Rochester, NY 05.2001 -
Skills
Xilinx Vivado
IP core development
VHDL
Verilog/SystemVerilog
HDL debug
Static timing analysis
Embedded C
Petalinux
TCL scripting
Python
Java
Communication
Interests
Timeline
Senior FPGA Design Engineer
Vanteon
05.2021 - Current
Engineering Intern
Vanteon
05.2020 - 08.2020
Research Lab Intern
Rochester Institute of Technology, RIT
05.2019 - 08.2019
Engineering Intern
Techwell Consulting
05.2018 - 08.2018
Bachelor of Science - Computer Engineering
Rochester Institute of Technology
05.2001 -
Master of Science - Computer Engineering
Rochester Institute of Technology
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