David Sauer
Tigard,OR
Summary
Detail-oriented, organized and meticulous employee. Works at fast pace to meet tight deadlines. Enthusiastic team player ready to contribute to company success. Competent Engineering professional offering foundation in engineering project management and design. History of success in performing
Overview
30
30
years of professional experience
Work History
Wet Etch Supply Chain R&D Engineer
Intel Corporation
05.2013 - Current
- Materials owner for Wet Etch Cleans chemical development and supply chain management
- Presented technical findings to stakeholders, ensuring clear understanding of project status and goals.
- Achieved successful project outcomes by maintaining accurate documentation and meeting strict deadlines.
CMP Materials Technical Supplier Owner
Intel Corporation
05.2011 - 05.2013
- Supplier and development owner for Backend Copper and Barrier Slurries and Post CMP Cleans.
- Proactively identified areas of risk within the supply chain and implemented necessary safeguards mitigating any potential negative impact chemical quality.
Senior Process Engineer
Intel Corporation
02.2009 - 04.2011
- Integrated into Far Backend Lithography and became the Reticle and Stepper alignment system expert
- Spearheaded technology transfer activities, ensuring smooth production scale-up from pilot plant to full-scale manufacturing operations.
- Improved product quality by conducting root cause analysis on process deviations and implementing corrective actions.
Senior Staff Engineer
Intel Corporation
08.2006 - 02.2009
- Led task forces to solve urgent problems
- Developed and managed high profile process changes to improve yield, cost, and cycle time
- Mentored junior engineers and provided coaching for engineering group leaders.
Group Leader – Electroplating, Wet Etch, and Oxide/W CMP
Intel Corporation
10.2002 - 08.2006
- Directly managed small teams of engineers responsible for ramping newly developed processes into HVM
- Developed and managed cost reduction initiatives, and process enhancements.
Senior Process Engineer – CVD, Electroplating, Oxide CMP
Intel Corporation
09.1994 - 10.2002
- Lead engineer responsible for equipment performance in tungsten CVD, Oxide CMP, Copper Electroplating and Copper CMP
- Improved process capability and hardware reliability.
Education
PhD - Chemical Engineering
University of Washington
Seattle, WA09.1994
BS - Chemical Engineering
University of Wisconsin
Madison, WI05.1989
Skills
- Materials/Process Development
- Customer Orientation
- Process Analysis, Evaluation & Troubleshooting
- Problem Solving
- Team Building & Leadership
- Data Analysis
- Strategic Planning & Execution
- Root Cause Analysis
- Process Improvement
- Project Management
- Technical reporting
- Process Development
Activities
- University of Washington Capstone Project, 2007, 2008, Provided a problem definition for MSE student’s senior project Mentored the students through the process of completing the project
- Oregon State University – Oregon Metals Initiative, 2008, 2009, Provided research ideas for chemical engineering students Coached students through experimental design and data analysis
Awards
- Materials - Divisional Recognition Award, Barrier Slurry development to Replace PFOA Containing Slurry, 2012
- Technology & Manufacturing Group – Excellence Award, Integrating Low-K Dielectric with Flip Chip Packaging, 2004
- Logic Technology Development – Divisional Recognition Award, Development of Cu Edge Bead Removal Process, 2001
- Logic Technology Development – Divisional Recognition Award, Qualification and Implementation of In-Situ CMP Metrology, 1999
- Fab, Sort & Manufacturing – Divisional Recognition Award, Elimination of Spongy Via Defect, 1997
- Fab, Sort & Manufacturing – Divisional Recognition Award, Development and Implementation of Improved Oxide Planar Process, 1996
- Fab, Sort & Manufacturing – Divisional Recognition Award, Finding Root Cause and Eliminating Tungsten CVD defect, 1995
Birding, Hiking, Tinkering
Love to get outdoors and explore the wilderness looking for and listening to birds. When the weather is too nasty to go outdoors i love tinkering in the garage
Timeline
Wet Etch Supply Chain R&D Engineer
Intel Corporation
05.2013 - Current
CMP Materials Technical Supplier Owner
Intel Corporation
05.2011 - 05.2013
Senior Process Engineer
Intel Corporation
02.2009 - 04.2011
Senior Staff Engineer
Intel Corporation
08.2006 - 02.2009
Group Leader – Electroplating, Wet Etch, and Oxide/W CMP
Intel Corporation
10.2002 - 08.2006
Senior Process Engineer – CVD, Electroplating, Oxide CMP
Intel Corporation
09.1994 - 10.2002
PhD - Chemical Engineering
University of Washington
BS - Chemical Engineering
University of Wisconsin