Deepak Musuwathi Ekanath
Engineer
Austin,TX
Overview
13
13
years of professional experience
1
1
Certification
Work History
Data Center Quality Engineer - ML/GPU Platforms
Google Inc.
Austin, TX
09.2025 - Current
- Strategic Quality gatekeeper for Google's global data center and mission critical AI/ML GPU Platforms, vetting and mandating standards for multi billion dollar hardware and software investments.
- Develop and deploy advanced quality models to lead high stakes failure investigations, driving systemic corrective actions and guaranteeing non-negotiable business continuity for Google's AI leadership.
SoC Product Development Engineer
ARM Inc.
Austin, TX
06.2023 - 08.2025
- Program manager for establishing a Yield management system for post silicon data and delivered the solution hitting the cost, features and performance requirements.
- Established a data driven and efficient die selection methodology using Foundry WAT data parameters, leading to improved characterization results.
- Established data driven methodologies including Power performance, power modeling, Yield Analysis, die matching.
- Developed robust set of characterization parsing and plotting tools, dashboards and automated reports for core Power Performance Architecture characterization of ARM ELP cores and mixed signal IPs on 3nm and 2nm nodes.
- Established and improved methodologies for Pre-silicon simulation to post silicon ATE characterization data correlation.
Product Engineer - ATE
NXP Semiconductors Inc.
Austin, TX
07.2021 - 05.2023
- Qualified 64 bit test hardware using volume data analysis which improved the accuracy by ~1.25x.
- Developed a robust methodology to group pins during testing that improved the overall test flow and maintaining the same level of quality to enable Zero defects policy.
- Debug and improvement of temperature calibration diodes consistency of performance over the temperature range per specifications to shorten the qualification process.
- NPI Qualification of Automotive Products by test development, integration and Data collection of Mixed signals, System on Chip (SOC) Final Test packaged parts using Teradyne testers.
- Characterization and model building of analog test parameters across PVT corners which eliminated the need for other volume data collection steps, thereby improving the module test time by ~5%.
Product Engineer - Post Silicon Analog/Design Validation
IM Flash Technologies/Micron Technology Inc
Lehi, UT
07.2018 - 06.2021
- Successfully led the probe program releases for 3DXP products, improving the yield, reliability and quality of the product, leading to the completion of JDP program between Intel and Micron.
- Characterize, validate and develop rigorous test plans for Memory devices, along with Engineering test program development using C++ to screen back-end of the line or reliability failures, both on CMOS and Array, before they are converted to baseline.
- Test and analyze the data from the ATE/bench and HTOL for proper characterization of silicon at wafer level, Final test and System Level Testing and share the learning across cross functional areas.
- Creation of standardized Python and Perl bench scripts and distribution of the same using Version Control software (GIT and SVN) to be used for worldwide teams, that improved the efficiency of bench data collection process by at least 2x.
- Develop testing methodologies to detect product failures at different phases and screen them at Front end Probe, thereby reducing the overall DPM close to 1200x.
- Analysis of the logics and circuits using Cadence Virtuoso to identify the physical and electrical failure analysis and Electrical isolation and collaborating with Yield Enhancement team in cross sectioning and imaging using FIB, SEM and TEM.
- Utilized data analysis skills and pareto method to troubleshoot and root cause deviations that led to substantial cost reduction.
- Reliability prediction and improvement using Weibull and binomial distribution and analysis.
- Automation of data analysis using JMP and Python that saved at least 10 hours/week.
Yield Enhancement Engineer
IM Flash Technologies/Micron Technology Inc
Lehi, UT
08.2012 - 06.2018
- Responsible for creating robust, reliable and repeatable recipes for the HMI eBeam inspection tools, that were used for yield and process improvement.
- Improved SNR of the inspection recipes by an average of 32.5x on all inspection levels using Design of Experiments, Root cause analysis, Sourcing techniques.
- Collaborate with the Fab processing areas, including Process Integration, Photolithography, Dry Etch, CMP, in design of experiments and data collection for the experiments, reporting on the findings to enable better decisions, also expediting the learning by at least 30-45 days.
- Creation of inspection recipes to detect electrical defects that were previously not detected using other inspection tools, thereby pushing the boundaries of traditional inspection methodology.
- Validation of the inspection recipes by collaborating with Yield Enhancement team for SEM and TEM images and inline FIB for imaging.
- Develop Machine Learning Algorithms to automatically classify defects that were detected using other UV and optical inspection tools.
Education
Master of Science - Electrical Engineering
University of Houston
01.2012
Bachelor of Engg - Electronics & Communication Engg.
Mepco Schlenk Engineering College
01.2010
Skills
- Electrical - Teradyne UltraFlex
- Magnum
- UF3000 ATE testers
- Circuit Analysis
- Simulation
- Schematic capture
- Signal tracing
- Corner case testing
- Voltmeters
- Oscilloscopes
- ESD-Latch up
- Process improvement
- Design of experiment
- Six Sigma methodologies
- 8D methodologies
- CPK improvement
- Quality and Reliability analysis
- Gauge R&R
- Measurement System Analysis
- Programming
- Python
- Perl
- JSL
- C
- Data Analysis
- Statistical Process Control
- Regression/Correlation analysis
- ANOVA
- PCA with JMP
- Outlier detection and analysis
- Data science/ML
- NN
- SVN
- Bootstrap Forest Tree
- Naïve- Bayes
- Principal Component Analysis
- Project management
- Jira
- Gantt chart
- PERT
- CPA methodologies
- Contingency planning
- Resource allocation
- CAPA development
- New Product/Technology Introduction (NPI/NTI)
Certification
- ASQ Certified Six Sigma Black Belt
- KT Problem Solving and Decision Making
Expertise
Teradyne UltraFlex, Magnum, UF3000 ATE testers, Circuit Analysis, Simulation and Schematic capture, Signal tracing, Corner case testing, Voltmeters, Oscilloscopes, ESD-Latch up, Design of experiment, Six Sigma methodologies, 8D methodologies, CPK improvement, Quality and Reliability analysis, Gauge R&R, Measurement System Analysis, Python, Perl, JSL, C++, Statistical Process Control, Regression/Correlation analysis, ANOVA, PCA with JMP, Outlier detection and analysis, NN, SVN, Bootstrap Forest Tree, Naïve-Bayes, Principal Component Analysis, Jira, Gantt chart, PERT and CPA methodologies, Contingency planning and resource allocation, CAPA development, New Product/Technology Introduction (NPI/NTI)
Publications
- D. Musuwathi Ekanath, Nacer Badi, Abdelhak Bensaoula, Modeling and Simulation of Artificial Core shell nano particles for Electrostatic Capacitor Applications, COMSOL Conference, Boston, 2011-10-01
- D. Musuwathi Ekanath, M. Crain, A Statistical Approach To Grouping Pins During Testing To Achieve Optimized Test Limits, TestConX 2023, Mesa, 2023-03-23, (Best Poster Award)
Timeline
Data Center Quality Engineer - ML/GPU Platforms
Google Inc.
09.2025 - Current
SoC Product Development Engineer
ARM Inc.
06.2023 - 08.2025
Product Engineer - ATE
NXP Semiconductors Inc.
07.2021 - 05.2023
Product Engineer - Post Silicon Analog/Design Validation
IM Flash Technologies/Micron Technology Inc
07.2018 - 06.2021
Yield Enhancement Engineer
IM Flash Technologies/Micron Technology Inc
08.2012 - 06.2018
Master of Science - Electrical Engineering
University of Houston
Bachelor of Engg - Electronics & Communication Engg.
Mepco Schlenk Engineering College