Spencer Offenberger
San Jose,CA
Summary
Qualified Staff Verification Engineer, with strong background in design verification engineering. Proven track record in developing and implementing verification strategies that enhance product reliability across a variety of projects and IP's. Demonstrated ability to troubleshoot complex systems and collaborate effectively with cross-functional teams.
Overview
11
11
years of professional experience
Work History
Staff Design Verification Engineer
Qualcomm (Adreno)
Santa Clara, CA
01.2023 - Current
- Lead full-chip preemption testing project across Android/Windows, enabling that feature (2 project tapeouts)
- Worked on feature implementation across 3 projects within the SP related to checkers and infrastructure
- Owned checkers that validated the shader execution in verilog at runtime and owned and developed an offline checker that would use python to do similar checks for higher level debugs
- Debugged issues found in block, top, emulation and post-silicon using the checker infrastructure developed and owned in python
- Helped close coverage for new features and legacy features inside the shader processor
Design Verification Engineer
Google (Gchips)
Mountain View, CA
01.2022 - 01.2023
- Worked on crypto accelerator at SoC/IP level & register/memory firewall
- Validated implementation of the initial bringup and compliance of algorithms using both verilog randomization and python stimulus generation to match cryptography compliance
- Created UVM components & sequences to test functionality
- Created C++ tests for functional, low power, warm reset scenarios
Senior Design Verification Engineer
Qualcomm (Adreno)
Santa Clara, CA
01.2019 - 01.2022
- Lead verification on ALU and read only cache within shader processor
- Implemented new features, created testplans, and closed coverage
- Created UVM testbench and closed initial ray tracing ASIC
- Implemented complex logic for ray tracing specific test randomization, brought up basic blocks with formal tools, implemented testbench for multiple components for bringup and closure
Windows Display Driver Intern
Nvidia
Santa Clara, CA
01.2018 - 01.2018
- Worked on HDR and new display feature bring-up of new GPU
Design Verification Engineer Intern
Intel
Chandler, AZ
01.2015 - 01.2017
- Worked on various components for UVM testbench (Xeon)
- Created and debugged x86 testing for CPU testbench (Atom)
Education
M.S. - Computer Engineering
University of Illinois
Urbana-Champaign, IL05-2019
B.S.E - Electrical Engineering
Arizona State University
Tempe, AZ05-2017
Skills
- System Verilog
- Python
- UVM
- Computer Architecture,
- Coverage
- Test Planning
- Formal Verification
- C
- GPU Architecture
- Linux
- TCSH/Bash
Timeline
Staff Design Verification Engineer
Qualcomm (Adreno)
01.2023 - Current
Design Verification Engineer
Google (Gchips)
01.2022 - 01.2023
Senior Design Verification Engineer
Qualcomm (Adreno)
01.2019 - 01.2022
Windows Display Driver Intern
Nvidia
01.2018 - 01.2018
Design Verification Engineer Intern
Intel
01.2015 - 01.2017
B.S.E - Electrical Engineering
Arizona State University
M.S. - Computer Engineering
University of Illinois