Lopamudra Sen
Concord,MA
Summary
Seeking challenging career opportunities in VLSI design & Verification domain with an organization of repute.
A competent professional with 11 years of experience in Hardware Design & Verification industry with expertise in Formal and Functional Verification technology. Currently responsible for IP level verification by defining the verification scope, developing the verification infrastructure, test suites and verifying the correctness of the design. Knowledge of all phases of ASIC design methodology. Made strong contributions to successful tape outs of multiple SOCs - using simulation based verification methodologies, formal verification and dynamic Assertion based verification. Knowledge on multiple verification methodology - OVM, UVM. Knowledge on Bus Protocols like AXI, APB and communication protocol like Ethernet Protocol. Familiarity with ARM architecture. Excellent debugging and problem-solving skills.
Overview
18
18
years of professional experience
Work History
Staff Engineer
Qualcomm
San Diego, USA
09.2017 - Current
- Executed verification cycles on a variety of digital designs, ranging from small blocks to large SoC's.
- Collaborated closely with designers to identify bugs early in the development cycle through debugging techniques such as waveform viewing or logic analyzers.
- Developed test plans and strategies for verifying design integrity of integrated circuits.
- Contributed towards improving existing processes around regression setup and execution which resulted in faster time-to-market delivery.
- Participated actively in cross-functional meetings with Designers and Architects providing feedback on design decisions.
- Utilized UVM methodology for building verification environment components like drivers, monitors.
- Created assertions to check different properties at RTL level during simulation runs.
- Performed functional coverage analysis to ensure all functionality was tested in the design verification process.
- BFM Modelling for custom Protocol to verify different design interfaces
Lead Verification Engineer
Aricent
Hudson, MA
08.2016 - 09.2017
- IP level verification: The goal of this project is to verify an IP for Intel's 3D Memory Controller.
- Analyzed test results, identified defects and communicated findings to design teams.
- Developed scripts for automation of tests using Python, TCL and C++ languages.
- Documented system behavior through debugging logs and diagrams for further analysis.
- Created regression tests to assess the impact of changes made to existing systems.
Senior ASIC Engineer
SanDisk
Bangalore, India
01.2015 - 07.2016
- Assertion Based Verification: I have applied assertion (System verilog assertions (SVA) and property specific language (PSL)) to verify the temporal relation of output signals with respect to inputs.
Senior ASIC Engineer
Rockwell Automation India
Noida, India
02.2011 - 01.2015
- Verification of Multiport Ethernet Switch for an SoC.
Verification Engineer
Interra Systems India
Noida, India
08.2006 - 02.2011
- SoC Level Verification: The assignment is to verify the DFT logic used in one of the major SoC in Texas Instruments.
Skills
- Functional Verification Tools: Incisive Enterprise Solution (Cadence design systems), VCS ( Synopsys’)
- Formal Verification Tools: Incisive Formal Verifier (Cadence's), VC Formal (Synopsys’s), Jasper Gold
- Others: CVS, Makefile, GIT, SVN, Doxygen
- Hardware Description language: Verilog
- Hardware Verification language: System Verilog
- Assertion language: PSL, SVA
- Programming language: C, C(beginner)
- Scripting language: Perl, Shell
- Linux, Unix
- Windows
Career Achievements
- Awarded with Aricent Kudos for outstanding performance at Intel in April 2017.
- Awarded with outstanding performance recognition certificate from Rockwell Automation for putting exceptional effort in one of the critical controller ASIC Verification on June, 2012.
- Received “Flamingo Award for Excellent Professional Attitude” for excellent service in Texas Instruments SoC verification project in Oct-09.
- Awarded with Interra trophy for showing technical excellence and dedication in Formal Verification project for Texas Instruments in 2009
- Awarded spot bonus two times for significant contribution to Interra Systems’ growth for working with Texas Instruments and Carbon Design system projects
- Received “BEE Award for best team” for outstanding performance
Websites
Academia
College of Engineering & Management, Kolaghat, B. Tech. (Electronics & Instrumentation), 8.26 out of 10, 2006, Bethune Collegiate School, West Bengal Board, 78.1%, 2002, Bethune Collegiate School, West Bengal Board, 82%, 2000
International Papers Publications
- A Paper on "Complete DFT RTL Verification Using Formal Techniques for Complex SoCs" at DAC'2010
- A Paper on "DFT Logic Verification through Property Based Formal Methods – SOC to IP" has been published at FMCAD in 2010
- A paper on “Formal verification of EFUSE Controller – A Case Study” has been published at 2008 IC Design and Verification Conference (ICDV)
- A Paper on “Formal Verification of P1500 Entry Sequence and connectivity” has been published at DSPS/SDTC Tech day in 2008
- A White paper on “Verification of Packet Arbitration in Multiport Ethernet Switch through output Queuing”.
Work Profile
- Working as Staff Engineer at Qualcomm from September 2017.
- Worked as Lead Verification Engineer at Aricent from August 2016 to September 2017.
- Worked as Senior ASIC Engineer in SanDisk, Bangalore from Jan 2015 to August 2016
- Worked as Senior ASIC Engineer in Rockwell Automation India, Bangalore since February 2011 to Jan 2015
- Started career as Verification Engineer in Interra Systems India working for client Texas Instruments between September 2006 till Feb 2011
Timeline
Staff Engineer
Qualcomm
09.2017 - Current
Lead Verification Engineer
Aricent
08.2016 - 09.2017
Senior ASIC Engineer
SanDisk
01.2015 - 07.2016
Senior ASIC Engineer
Rockwell Automation India
02.2011 - 01.2015
Verification Engineer
Interra Systems India
08.2006 - 02.2011