Divya Gupta
Foxborough,MA
Summary
PDK Engineer with 4+ years of experience in utilizing various software tools and languages to create, design, automate and debug IC designs. Solid understanding of device physics and FinFET technology and Runset Development. Experienced in industry standard tools such as Cadence Virtuoso and Calibre. Applying to this position to leverage my knowledge and expertise in semiconductor industry.
Overview
7
7
years of professional experience
Work History
Sr. Design Engineer/ Technical Leader
Sevya MultiMedia
10.2020 - 01.2023
- Managed team of 6 people from various technical backgrounds- provided basic training and regular project support and feedbacks
- Developed and validated DRC design rules/ ruledecks/ runsets based on Design Rule Manual (DRM) requirements for 7 process nodes
- Coordinated and sometimes performed QA plans, drive testcase development working with relevant stakeholders using CADENCE or MENTOR GRAPHICS layout tools
- Worked with OPS technology in TCL for better data extraction from DRM
- Working experience with Perl
- Performed detailed evaluation of tool run results to validate proper tool behaviour and identify the cause of any discrepancies found
- Developed and enhanced automation software and scripts for tool regression and collateral generation, including quality check and testing by running on relevant decks and verifying no impact in CALIBRE DRC, ERC, LVS, reports
- Managed tickets- reproduce, analyse, debug, provide solutions, test and integrate, close the ticket.
Sr. EDA Engineer
Vicor Coporation
02.2024 - Current
- PDK Development - Foundry Support, LVS and DRC, Cohesion to Cadence conversion.
- Tool Support and Integration - Integrating 3rd party tools into existing Design Tools eg Cliosoft, License Management, Integration of cell libraries from Foundries.
- Maintaining File Servers in Linux and interface with Vicor IT. Putting in place methodologies and trainings for positive adoption by design team.
Silicon Design Engineer II
AMD
12.2018 - 09.2019
- Catered to in-house scripting and automation environments (i.e., TileBuilder) within the CAD team of 5
- Created 5 scripts in perl to communicate with existing interface to produce expected results, integrate in the environment after rigorous testing across multiple projects
- Engaged with internal partners and EDA vendors to coordinate tool feature requirements and specifications, which would increase performance by 15%.
Physical Design Engineer
Intel
01.2017 - 12.2017
- Experience in analog/mixed-signal layout design of deep submicron CMOS circuits and on advance nodes including FinFET technologies
- Learn the inhouse layout tool GenA and build 20 layouts for small cells/ blocks
- Gained knowledge on industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Automatic Place & Route (APR), Power Distribution and Pin Placement
- Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
- Managed tickets - reproduce the errors, analyse and provide a working solution, integrate into the system and close the ticket within deadlines.
Education
Master of Science -
University of Texas at San Antonio
San Antonio, Texas01.2016
Bachelor in Engineering -
Shri Govindram Seksaria Institute of Technology and Science
Indore, M.P.01.2013
Skills
- SVRF
- Perl
- Tcl
- DRC
- LVS
- DRM
- Device physics
- CalibreDRC
Timeline
Sr. EDA Engineer
Vicor Coporation
02.2024 - Current
Sr. Design Engineer/ Technical Leader
Sevya MultiMedia
10.2020 - 01.2023
Silicon Design Engineer II
AMD
12.2018 - 09.2019
Physical Design Engineer
Intel
01.2017 - 12.2017
Master of Science -
University of Texas at San Antonio
Bachelor in Engineering -
Shri Govindram Seksaria Institute of Technology and Science