Elvis Chen
Camas,WA
Summary
Detail-oriented individual with exceptional communication and project management skills. Proven ability to handle multiple tasks effectively and efficiently in fast-paced environments. Recognized for taking proactive approach to identifying and addressing issues, with focus on optimizing processes and supporting team objectives.
Overview
24
24
years of professional experience
Work History
Senior Process Optimization Engineer
TSMC Washington
Camas, WA
05.2021 - Current
- Analyze and interpret sort testing data. Provide solutions to improve test accuracy.
- Optimize semiconductor device yield for consumer/ automobile applications including ambient light sensor, flash memory and MEMS.
- Resolve bonding pad opening issue up to 10% yield improve.
- Resolve Top-Metal bridging issue up to 40% yield improve.
New Technology Developing engineer
Robert Bosch (former TSI Semiconductors)
Roseville, CA
12.2016 - 05.2021
- Developing new process for BOEL thin-film resistor and RF-MEMS.
- Designs electrical test structure for BEOL thin-film resistor.
- NTO project success: 750V HV-CMOS RAD-Hard transistor
- NTO project success: 1.8V/5V/20V with BEOL thin-film resistor
- Resolved chamber arcing issue for RF-MEMS product line up to 40% yield improve.
Sensor Developing Engineer
TSMC
Taiwan
04.2012 - 12.2016
- Design electrical test algorithm for optical images sensor characterization
- Reduce silicon crystal damages and effectively improve the dark current from 10K electrons/ sec to less than 10 electrons/ sec
- Evaluate photodiode design scaling concept and successfully improve full well capacity twice. (from 3000 electrons to 6500 electrons)
- Developing process of high-absorption layer and successfully improve quantum efficiency to 25% at near-IR region.
Process integration engineer
TSMC
Taiwan
08.2008 - 04.2012
- Coordinate new product introduction in 300mm giga fab. Improve device uniformity, device window optimization and resulted in 5% yield improve (defect density D0<.04).
- FAB tools: SEMvision, FX-100, NOVA, CDSEM and film matrix
- LAB tools: SRP, 4PP, SEM, FIB, EDX, UV-vis-IR, SEM, TEM, EMMI
- Big data analysis: JMP Statistical Software
- Layout design: Ledit, cadence
Associate integration Engineer
Vishay-General Semiconductor
Taiwan
09.2000 - 07.2002
- Conducted new product developments including new masks tape out, prototype sample preparation, electrical and qualification test
- Designed silicon process flow for fast-recovery diode, schottky diode and transit voltage suppression (TVS)
- Identifying device failure device by SRP (Spreading resistance profiling), optical microscope, 4-points probe and curve tracer.
Education
Master - Materials Engineering
University of Texas
Arlington12.2006
BS - Chemical Engineering
TATUNG University
Taipei09.1998
Skills
- Problem-solving skill
- JMP, statistics data mining and analysis
- Semiconductor device performance improve
- Test algorithm development
Phone
mobile, 425-236-3470
Personal Information
Title: Semiconductor technology developing engineer
Additional Information
US citizens
Timeline
Senior Process Optimization Engineer
TSMC Washington
05.2021 - Current
New Technology Developing engineer
Robert Bosch (former TSI Semiconductors)
12.2016 - 05.2021
Sensor Developing Engineer
TSMC
04.2012 - 12.2016
Process integration engineer
TSMC
08.2008 - 04.2012
Associate integration Engineer
Vishay-General Semiconductor
09.2000 - 07.2002
Master - Materials Engineering
University of Texas
BS - Chemical Engineering
TATUNG University