Gabriel Bujanda

Responsible for various process integration/technology expertise supporting ASIC product design and integration, implementing quality and manufacturing standardization methodologies, lead cross-functional teams in support of process improvement

• Provide structured, model-based problem-solving leadership and facilitation to resolve center wide technical issues improving impacts to post fabrication packaging yield to less than 0.1% and doubled post fabrication test capacity
• Provide program lead back up for heterogeneously integrated low orbit detectors delivering flight quality assemblies to the customer by analyzing post fab test data, ensuring quality systems are in place and process flows are maintained and optimized
• I continue to own development activities in support of the next-gen rad hard CMOS process enabling the next level milestones for technology maturation and technical troubleshooting for ongoing and emerging yield and performance problems
• In addition, I provide technical and leadership mentoring to early career staff to foster continued growth in their technical expertise, communication, experimental design, and problem-solving effectiveness
• Enhanced data accuracy through the development of automated processes to validate and synchronize information between systems.
• Collaborated with cross-functional teams to identify requirements, design solutions, and deliver integrated devices that met business needs.
• Facilitated knowledge transfer among team members by creating comprehensive documentation on integration processes and best practices.
• Conducted regular post-implementation reviews to evaluate the success of integration projects and identify areas for improvement.
• Collaborated with cross-functional teams to identify requirements, design solutions, and deliver integrated systems that met business needs.
• Liaised with production support team to coordinate production issues and opportunities for improvement.
• Established strong working relationships with stakeholders across multiple departments to facilitate collaboration on technology improvement initiatives.

• Responsible for process, maintenance, sustaining, and development activities for ND/National Security Rad Hard CMOS ASIC production, advanced node Rad Hard CMOS, and micro-electronic research and development
• This includes responsibilities for both tactical and strategic fab operations from facilities to final wafer production, with a specific focus on advanced CMOS process development and yield improvement
• The role also involves developing new strategic initiatives for future work within the labs and with external government agencies
• I lead, grow, and direct the work for the for the lithography, dry etch, wet etch and chemical/mechanical polish process engineering teams as well as the team responsible for monitoring, sustaining, and improving process and product yield. In this time the team improved the yield of our main product by 30%.
• In addition, my role involves future fab sustainment with new tool capability procurement and planning and executing facilities upgrades. My team was responsible for the pathfinding, procurement, installation, and qualification of multiple state-of-the art metrology tools.
• Managed and motivated employees to be productive and engaged in work.
• Maintained professional, organized, and safe environment for employees and customers.
• Resolved staff member conflicts, actively listening to concerns and finding appropriate middle ground.
• Cross-trained existing employees to maximize team agility and performance.
• Developed a strong company culture focused on employee engagement, collaboration, and continuous learning opportunities.
• Built high-performing teams through effective recruitment, onboarding, and talent development initiatives.
• Maintained positive customer relations by addressing problems head-on and implementing successful corrective actions.
• Leveraged data and analytics to make informed decisions and drive technology improvements.

• Responsible for sustaining process and device performance during 6” ramp down and process development and matching for 8” start up on the CMOS7 program
• Became one of the lead integrators on HTS-MEO program, led the team responsible for a complex 6” motherboard production run, and owned the defect limited yield improvement efforts for the Sandia-Skorpios partnership on the DSP product
• In addition, have led the development activities for the SEU resistor and contact etch/fill on CMOS8 and participated in the beyond 180nm LDRD exploring new gate stack materials and processing
• Performed acting L1 duties in 05252 providing coverage for current manager for approximately 1 month
• Successfully managed multiple projects simultaneously by setting clear goals, prioritizing tasks, and monitoring progress.
• Developed comprehensive documentation for designs, including schematics, calculations, specifications, and reports for review by clients or regulatory agencies.

• Managed the Front End Metals Process Engineering group comprised of 6 senior and 5 junior engineers and was responsible and accountable for engineering development, module quality and output, resource coordination and stakeholder management for process and yield improvement projects across 7 toolsets
• Received intensive management training from the NeuroLeadership Institute and is well versed in the SEEDs model for breaking bias and SCARF model for improving employee engagement by fostering a growth mindset
• Reduced product defects with thorough root cause analysis and implementation of corrective actions.
• Mentored junior engineers on best practices in process engineering management, fostering a culture of collaboration and professional growth.
• Managed cross-functional teams to achieve project milestones, ensuring on-time delivery of high-quality products.
• Presented key performance indicators at executive-level meetings, showcasing departmental accomplishments and aligning stakeholders on strategic goals.
• Coordinated maintenance activities with operations teams to minimize disruption to production schedules while ensuring equipment reliability.
• Implemented statistical process control techniques to monitor product quality and improve overall yield rates.

• Responsible for front end process integration and technical expertise in multiple segments of advanced 90, 45, and 32nm semiconductor logic transistor manufacturing including contact patterning, metal gate replacement, thin films deposition, device/materials characterization, and all relevant impacts to transistor device behavior
• Also, responsible for device performance targeting and process health to meet customer supply needs
• This involved modeling physical transistor parameters with device speed and leakage to optimize product performance
• Advanced skills in model-based problem solving (MBPS), data analysis (including statistical data mining techniques and analysis using JMP and other related software packages), design of engineering experiments (DOE), and overall MOS device physics (focus of master’s degree study) and operation including modeling using SILVACO platform
• Led and managed several high-level technical teams at the local and cross-factory level including the virtual factory segment team responsible for yield improvement and change control, the 32/45nm Performance Targeting Team consisting of representatives from all key modules and was the chair of the 32/45nm Process Change Control Board all between 2006-2017
• Improved device performance by optimizing design and implementing advanced engineering techniques.
• Enhanced production efficiency through streamlining manufacturing processes and reducing material waste.
• Delivered executive level updates on technology status.
• Analyzed and developed innovative resolutions for complex problems.
• Developed innovative solutions for complex device issues, resulting in increased customer satisfaction.
• Trained junior engineers in device engineering best practices, fostering a culture of continuous improvement within the team.