Detail-oriented and results-driven ASIC Design and Verification Engineer with nearly two years of hands-on experience. Proven expertise in SystemVerilog, UVM, Python, C++, and EDA tools. Seeking a challenging role to apply technical skills in RTL design, Verification Methodologies, Software or Firmware application and collaborative problem-solving.
Proficiency: R&D, Digital Design, Computer Architecture, RTL Design, CPU and GPU architecture, UVM, Pre and Post silicon Verification, ASIC design Verification, Object-oriented programming (OOP), Application Programming Interface (API).
Languages: Python, C++, System Verilog, and Perl.
Tools: Git, Linux, VS Code, LPDEV, SDK, Verdi, Synopsys EDA, RISC-V, FPGA, and Microcontrollers (Raspberry Pi, Arduino Boards).