Summary
Overview
Work History
Education
SUMMARY
Accomplishments
Timeline
Generic

GIREESH VIJAYAKUMAR

Sunnyvale,CA

Summary

  • 3D Integration and Implementation: Expertise in 3D integration methodologies and execution. Adept at addressing hybrid bonding, die partitioning, signal integrity, thermal management, and cross-die power delivery challenges for AI designs.
  • Power Integrity Leadership: Extensive leadership in PDN methodology development, including grid weakness resolution, dynamic/static IR drop analysis, SignalEM, ESD, and inrush current challenges, leveraging tools such as Ansys RedHawk and Cadence Voltus.
  • Advanced Technology Node Enablement: Proven ability to evaluate and deploy advanced technology nodes by conducting PPA trade-off analyses, assessing process maturity, and integrating cutting-edge nodes into design workflows.
  • SoC Leadership Expertise: Comprehensive experience in SoC design spanning 2nm–45nm nodes, covering end-to-end processes such as floorplanning, PnR, CTS, RC extraction, timing closure, and verification. Skilled at leading cross-functional teams to deliver high-performance, efficient designs.
  • End-to-End Flow Development: Proficient in developing and optimizing RTL-to-GDSII flows, automating processes to enhance efficiency and accuracy. Expertise with tools including Synopsys (ICC2, PrimeTime, StarRC, Formality, FC), Cadence (Genus, Innovus, Voltus, Sigrity, Celsius, Integrity), and Ansys (RedHawk, Totem, Pathfinder).
  • Research and Innovation: Designed and implemented novel on-chip voltage sensing schemes in nanometer CMOS, addressing advanced challenges in power integrity and signal management.

Overview

16
16
years of professional experience

Work History

Silicon Physical Design Lead

Meta Platforms ( AI Silicon )
Sunnyvale, CA
11.2023 - Current
  • Leading the 3DIC implementation for Meta AI chips on cutting-edge node, focusing on cross-die design partitioning, HCB allocation, power delivery optimization, signal integrity, and thermal management.
  • Drove the physical implementation of AI compute units from floorplanning to GDSII, focusing on achieving optimal performance-per-watt through power-aware PnR strategies, efficient power grid design, design feedback to architecture teams, and post-silicon collaboration to refine performance and power metrics.
  • Led vendor collaborations to ensure alignment on design objectives and successful IP integration, meeting area, power, and performance goals.

Physical Design Methodology

Meta Platforms ( Reality labs )
Sunnyvale, CA
11.2021 - 11.2023
  • Developed and automated end-to-end RTL-to-GDSII flows, leveraging industry-standard tools to enhance execution efficiency and maintain quality.
  • Led pathfinding for future AR chip generations, conducting thorough evaluation of PPA comparisons, third-party IP availability, and overall NRE costs across diverse technology nodes.
  • Delivered robust power delivery network solutions across Meta AR chips, establishing scalable methodologies for IR/EM analysis, PG grid exploration, and power switch integration.

Senior Physical Design Engineer

Apple
Cupertino, CA
07.2018 - 11.2021
  • Executed PnR for multiple DDR blocks from netlist to GDS, developing recipes and methodologies to optimize power, performance, and area (PPA).
  • Served as the PDN/IR Lead for AMS, driving signoff processes through power grid exploration, analysis, and execution, and devising strategies to meet IR targets. Collaborated with cross-functional teams across Apple to ensure EMIR-clean IP delivery.
  • Led methodology improvements to streamline execution workflows and enhance quality metrics, reducing turnaround time while maintaining high design standards.

Staff Physical Design Engineer

Qualcomm
San Diego, CA
05.2013 - 07.2018
  • Executed PnR for multiple graphics blocks from netlist to GDS, including floorplanning, clock and power distribution, timing closure, and physical/electrical verification.
  • Served as the Graphics Team PDN/IR lead, driving signoff for graphics blocks by setting IR targets, exploring power grid options, and defining strategies for bump, decap, and switch placement.
  • Collaborated with the logic design team to understand partition architecture, ensuring early alignment of physical design aspects with the schedule and design goals.
  • Led PPA exploration for GPU blocks, identifying optimal solutions, and driving execution to achieve design objectives.
  • Developed automated flows and scripts for PDN and PnR to enhance execution efficiency and reduce turnaround time.

Physical Design Intern

Intel Corporation
Folsom, CA
05.2012 - 01.2013
  • PnR execution for a graphics partition which included synthesis, CTS, timing, physical and electrical verification.

Graduate Research Assistant

VLSI Circuits & Systems Group,UMass Amherst
Amherst, MA
08.2011 - 05.2012
  • Circuits for Accurate Voltage Drop/Droop Sensing: Thesis focused on designing and implementing novel digital on-chip voltage sensing schemes in nanometer CMOS.

Applications Engineer

ANSYS, Inc.
Bangalore, Karnataka
10.2008 - 08.2011
  • Product engineering and working with leading semiconductor design houses worldwide on cutting edge 45nm and below process technologies, to help adopt/integrate Apache tools into customer SoC CAD flows
  • Technical support for TIER-1 clients with activities like evaluations/benchmarks, silicon debug ,product training, flow development and foundry related support.
  • Lead developer of Apache’s flagship product RedHawk Explorer.

Education

Master of Science - Electrical and Computer Engineering

University of Massachusetts - Boston
Boston, MA
2013

Bachelor of Science - Electronics Engineering

Model Engineering College
2008

SUMMARY

16 years of experience in Physical Design, delivering high-performance SoCs at Meta, Apple, and Qualcomm. Expertise in 3DIC integration, PDN strategies, end-to-end SoC execution, and full-cycle collaboration with Architects, ASIC vendors, and EDA providers. Proven in developing RTL-to-GDSII flows and driving advanced technology initiatives. Currently contributing to Meta’s AI chip development with cutting-edge design methodologies and scalable silicon solutions.

Accomplishments

  • Patent Holder: Systems and Methods for Three-Dimensionally Stacking Systems on Chip with Face-to-Face Hybrid Bonding
  • Industry Presentation: Presented Meta’s Cadence Integrity 3D-IC prototyping solution to industry peers at CadenceLIVE, April 2024

Timeline

Silicon Physical Design Lead

Meta Platforms ( AI Silicon )
11.2023 - Current

Physical Design Methodology

Meta Platforms ( Reality labs )
11.2021 - 11.2023

Senior Physical Design Engineer

Apple
07.2018 - 11.2021

Staff Physical Design Engineer

Qualcomm
05.2013 - 07.2018

Physical Design Intern

Intel Corporation
05.2012 - 01.2013

Graduate Research Assistant

VLSI Circuits & Systems Group,UMass Amherst
08.2011 - 05.2012

Applications Engineer

ANSYS, Inc.
10.2008 - 08.2011

Master of Science - Electrical and Computer Engineering

University of Massachusetts - Boston

Bachelor of Science - Electronics Engineering

Model Engineering College

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GIREESH VIJAYAKUMAR