Gururaja Ghorpade
Aurora,USA
Summary
A motivated and versatile analog/mixed-signal circuit designer with a proven technical and managerial track record of a total of 20 years (after post-graduation - Master of Technology from IIT Kharagpur) experience in designing, building teams, and hands-on experience with high-performance, best-in-class analog/mixed-signal products and IPs, with knowledge of the end-to-end cycle from marketing requirements/concepts to silicon-proven successful volume production products. I have worked on low-power audio application products, gigabit Ethernet/automotive PHY products, data converter products, sensor analog front-end designs, PLL, phase interpolator, switched capacitor circuits, LDOs, bandgap references, and driving digital interface concepts, layout execution, foundry interaction/process node selection, and silicon bring-up and validation.
Overview
23
23
years of professional experience
Work History
Sr Manager Analog Mixed signal design
KNOWLES
Chicago, USA
10.2023 - Current
- Chip architect - Design and development of Low-power analog ASICs for analog MEMS microphone
- Sr Manager - Led a team of 11 engineers to design next-gen microphone ASIC, MEMS sensors and packaging with enhanced linearity and reduced noise performance for flagship products
- Leadership & Management: Cross-functional team leadership, strategic roadmap planning
- Vendor management – Collaboration and foundry management of ASIC and MEMS.
- Customer engagement – Successful design wins through continuous engagement with customers to meet the best suited microphone for their hearing aid systems.
- Knowles World Headquarter USA
Director
KNOWLES
Bangalore, India
09.2022 - 09.2023
- Provide leadership to all personnel at the facility.
- Engaged in Growing different product line teams to deliver multiple products
- Cross site collaboration for new product execution
- High performance, Low power & Low area ASIC used for Analog and digital ASICs for Microphone products: Working as Chip lead with cross functional team responsibility.
- Involved in discussions with different foundry (55nm to 300nm) to select suitable one to achieve target
- Involved in design of low power Amplifier along with MEMS interface
- Knowles India design center
Senior design Manager / Chip Lead + System Architect
MCE Group
03.2017 - 08.2022
- Building a strong self-sustainable team of design and layout to own and deliver products from India.
- Low power ASIC used for Analog Microphone products: Worked as Chip/Technical lead with cross functional team responsibility.
- Developed System level calculation and derived requirement specifications.
- Conceptualized new digital communication interface without any extra pad.
- Involved in design of low power Amplifier along with MEMS interface.
- Band gap reference and charge pump design.
- Design of temp sensor: Model and design of Incremental ADC & Fixed gain amplifier.
- Low power & Low area ASIC used for Digital Microphone products: Worked as Chip/Technical lead of these products.
- Developed System level calculation and derived requirement specifications.
- Design of low power Sigma delta ADC.
- Design of ASIC front end amplifier interfacing to MEMS.
- High voltage charge pump.
- Involved in designs of Power management blocks design: LDO’s, POR, Oscillators.
- IO design and ESD debugging.
- Responsible for Silicon Evaluation and support for wafer testing, Qualification and reliability.
- Key roles in silicon debugging for performance failure and ESD.
- Foundry communication and process node selection.
Senior Staff Engineer
MCE Group
05.2016 - 02.2017
- Low power ASIC used for Digital Microphone product (M17015).
- Driving platform creation project to different foundry and process node from 180nm to 130nm.
- Establishing new lab for Silicon validation.
- Strengthening the team and Mentoring.
- Successful first silicon.
Staff Engineer/ Gigabit Ethernet and Automotive connectivity Group
TEXAS INSTRUMENTS
Bangalore, India
09.2011 - 04.2016
- DP83867 & Family - Low Power Gigabit Ethernet Physical Layer Transceiver: 10/100/1000 MHz.
- Development and design of the clock scheme with the specified jitter.
- Modeling and design Implementation of 250MHz &1.25GHz PLLs for PHY and SGMII respectively.
- Modeling and Design Implementation of Phase interpolator circuit for CDR loop.
- Verilog-A modeling of sub blocks and responsibility of Analog Top level simulations.
- Responsibility of AMS simulations at chip level.
- Bench Evaluation.
- Product is in Market.
- Bangalore, India
Staff Engineer/ Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
Bangalore, India
10.2009 - 09.2011
- LMP90101: Ultra-low noise ΣΔ ADC, 0.35μm/3.3-5V.
- Worked for the design of Higher precision signal conditioner that includes a 24-bit, 3 channel ultra-low noise ΣΔ ADC with Programmable Gain 1x - 128x used in high precision measurements such as weigh-scale applications.
- Developed the modulator architecture to improve the NFR (noise free resolution) to 21 bits.
- Worked on CMOS design of switched cap modulator and executed changes required for input buffer.
- Design of CMOS relaxation oscillator required as internal oscillator.
- Implemented the design to support data rate up to 12KSPS.
- Worked with digital team in making the flexible input multiplexer to support all the new features.
- Bangalore, India
Senior Engineer/ Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
Bangalore, India
03.2006 - 10.2009
- LMP90100 and LMP9009x family: DC high precision ΣΔ ADC, 0.35μm/5V.
- LMP90100 Family is design of Sensor AFE system designed for Industrial Process Control, Strain gauge, Temperature and Pressure transmitter applications. LMP90097 is qualified for automotive applications.
- Developed and implemented the architecture of Analog Front-end design.
- CMOS design Implementation of flexible input multiplexer for channel selection.
- Implemented innovative CMOS Rail-to-Rail Input buffer to isolate sensors from switching load.
- Evaluated Innovative scheme of Modulator cap array get low gain error.
- Developed and implemented clock scheme for the complete system which includes Relaxation oscillator, Clock detect circuit and selection of clock source.
- Co-designer for background calibration techniques for gain and offset error correction and sensor diagnostics to detect open and short-circuit conditions and out-of-range signals, without requiring user intervention, resulting in enhanced system reliability.
- Involved in verilog-A modeling, AMS simulation, silicon bench evaluation using LABVIEW.
- Partially worked on the AMS simulation.
- Product is in the market.
- Bangalore, India
Senior Engineer/ System LSI- Analog
SANYO LSI
Bangalore, India
11.2004 - 03.2006
- Sub blocks design for Low Power Temperature Sensor 0.18μ/1.8V & 0.15u/1.5V.
- Generate the analog output voltage of 1.2 to 0.3v respective to the temperature from –30 to 1000C.
- Designed constant-gm circuit, Bandgap design. Project is in GSMC0.15u.
- Pipelined ADC, 0.18μ/1.8V.
- Designing Amplifier required for ADC.
- Bangalore, India
Design Engineer/ FPD Controller – Analog
UNITED MICROELECTRONC SOLUTIONS LIMITED
Bangalore, India
02.2003 - 11.2004
- Video Front Panel Controller (FPD) - 8 Bit 205MSPS ADC: 0.18μ CMOS TSMC-Process, 3.3V/1.8V.
- Active team player in deriving specification of front-end for ADC comprises of Clamping circuit, Single to Differential converter and Programmable Gain Amplifier.
- Design Implementation of 8bit 205MSPS ADC for digitizing the data.
- Implemented speed scaled down version of ADC 10bit 50MHz.
- Bangalore, India
Education
MTECH - Microelectronics and VLSI Design
INDIAN INSTITUTE OF TECHNOLOGY
Kharagpur, India01.2003
Skills
- Analog design
- Analog and mixed signal
- Chip architect and lead
- Low-power design
- Vendor management
- System architecture
- Product management
- Customer engagement
- team development
- Mentoring and leadership
Technical Summary
- Assessing design specifications: Low power Audio, Sensor AFE and Ethernet Products
- CMOS Analog Design: Data converters, Charge pump, LDO, PLL, RX, TX, Bandgap and reference designs
- Layout Execution
- Matlab Modeling
- VerilogA System Level Modelling
- AMS simulation: Chip level mixed signal simulations and verification
- Industry standard CAD tools and Linux/Unix environments.
- Top Level floor-planning and guiding Layout designers
- IO ring analysis for ESD/CDM/Signal integrity
- Bench characterization
- Technology exposure from 350nm to 65nm
- Mentoring and Cross functional interaction and multisite co-ordination
Personal Information
- Nationality: Indian
- Marital Status: Married
Hobbies and Interests
- Initiative to support Bangalore Kidney foundation
- Sports: Cricket, Table tennis
- Handling Analog courses during free time
Patent Details
- Zero wire interface communication to replace I2C, Under discussion, 01/01/25
- Microphone self-diagnostics through ASIC, Under discussion, 02/01/25
- Novel Start-up circuit for bandgap reference to mitigate the parasitic effect., Under process, IDF-00732, 01/01/23
- Digital microphone with over voltage protection., US 11,897,762B2d, 02/01/24
- Microphone with slew rate controlled buffer, US 11,909,387B2, 02/01/24
- Low voltage feedforward current assist Ethernet line driver, US20160072735A1, 09/10/15
- Background sensor diagnostic for multi-channel ADC, US8884629B1, 11/11/14
- Low noise, high CMRR and PSRR input buffer, US8330537 B1, 12/11/12
- Background Calibration Method for Fixed Gain Amplifiers, US8330631B2, 12/11/12
- Capacitor rotation method for removing gain error in sigma-delta analog-to-digital converters, US7825838, 11/02/10
- Background calibration method for ADC, US7825837, 11/02/10
Coursework
- Low power Low voltage designs for data converters by Dr. Andrea Baschirotto, Associated Professor, University of Salento
- CMOS Analog Circuit Design by Dr.Phillip E Allen, Professor, Georgia Institute of Technology
- ESD and Latch up protection by Dr.Phillip E Allen, Professor
- Workshop on CMOS (C9T5V) and BICMOS (ABCD5HV) by Dr.Phillip E Allen
Timeline
Sr Manager Analog Mixed signal design
KNOWLES
10.2023 - Current
Director
KNOWLES
09.2022 - 09.2023
Senior design Manager / Chip Lead + System Architect
MCE Group
03.2017 - 08.2022
Senior Staff Engineer
MCE Group
05.2016 - 02.2017
Staff Engineer/ Gigabit Ethernet and Automotive connectivity Group
TEXAS INSTRUMENTS
09.2011 - 04.2016
Staff Engineer/ Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
10.2009 - 09.2011
Senior Engineer/ Precision Signal Path Group
TEXAS INSTRUMENTS (NATIONAL SEMICONDUCTORS)
03.2006 - 10.2009
Senior Engineer/ System LSI- Analog
SANYO LSI
11.2004 - 03.2006
Design Engineer/ FPD Controller – Analog
UNITED MICROELECTRONC SOLUTIONS LIMITED
02.2003 - 11.2004
MTECH - Microelectronics and VLSI Design
INDIAN INSTITUTE OF TECHNOLOGY