Synopsys Yield Explorer
Harshavardhan Reddy Medasani
Yield And Diagnostics Engineer
San Diego,CA
Summary
Qualified Yield and Diagnostics Engineer proven to implement and maintain efficient methods of Yield analysis to improve Turn Around Time. Technically-savvy and skilled at quickly learning new concepts, software and equipment. Collaborative team player with excellent communication and interpersonal talents.
Overview
4
4
years of professional experience
6
6
years of post-secondary education
Work History
Yield and Diagnostics Engineer
Qualcomm
San Diego, CA
11.2019 - Current
- Validated and supported fab process BKM changes that reduced the production cost and time with negligible yield trade off.
- Assisted test teams in validating and implementing test vector move from wafer level to package level testing reducing wafer lever tester cost and time by 10% across all 4nm production.
- Conducted Chip Layout Analysis and Diagnostics to Layout Correlation to understand root cause (Cell/Net) driving Memory BIST and ATPG fails recovering Yield loss by 2% for 4nm Products.
- Analyzed and diagnosed stress test fails on 4nm major runner to help recover yield by 10% at stress.
- Collaborated with cross-functional teams to diagnose customer reported fails and pushed the foundry to implement a BKM recipe to avoid similar defects, improving the DPPM by 400.
- Created a standardized template to calculate Logic and Memory D0 (DPPM) of Mass Production Products for cross Product/BKM Comparison Analysis that improved root cause analysis efficiency by 20%.
- Tuned DOE Device Windows of multiple 6/5/4 nm Products and helped reduce device dependent Yield loss to baseline of ~4% across NONHV BINs.
- Analyzed COF data to identify outlier Core/s and drive Test/Process changes to reduce and recover yield loss of ~10% across multiple HV and NONHV BINs for 6/5/4 nm Products.
- Set up Statistical Process Control (SPC) to monitor Fab inline health through PCM and Metrology parameters and helped catch and diagnose outliers with 99% accuracy.
- Created Cognos Models to estimate the Future Monthly Yield Targets for multiple 5 and 4nm Mass Productions Products with an error margin of +/- 1%.
- Identified the root cause/s for Parametric fails after studying parametric data and driving the Test/Process changes to recover a yield loss of 2% on 5nm Products.
- Studied BIN Pareto to identify high failing BINs and followed up by Core/Test Vector Pareto Analysis to understand and debug root cause to recover Yield loss.
- Recovered MBIST NONHV Yield loss of 0.5% on multiple 4nm projects by identifying Test Program deficiencies through BIN and Core Pareto Analysis and driving the Test team to implement required Test Vector Changes.
- Implemented, validated and standardized a tool to capture EUV Mask Adder wafers with a hit rate of 98% (+/- 1%) and provide the estimated Yield impact.
- Developed a new FA Candidate communication platform between Diagnostics (Memory & Logic) and FA Lab (both Foundry and In House) that improved Turn Around Time by 30%.
Education
Master of Engineering - Electrical Engineering
University of Cincinnati
Cincinnati, OH 08.2017 - 04.2019
Bachelor of Science - Electrical, Electronics And Communications Engineering
Chaitanya Bharati Institute of Technology
Hyderabad, India 08.2012 - 05.2017
Skills
Data Analysis and Manipulation
Statistical Process Control
Logic and Memory Diagnostics Analysis
Layout Analysis
Product Yield Cognos Modelling
DFM and DFX analysis
DOE Window Analysis
BIN Pareto Analysis
Regression and Multi parametric analysis
Software
DataPower Exensio
Synopsys Avalon
Optimal Plus
Microsof Excel
JMP
Timeline
Yield and Diagnostics Engineer
Qualcomm
11.2019 - Current
Master of Engineering - Electrical Engineering
University of Cincinnati
08.2017 - 04.2019
Bachelor of Science - Electrical, Electronics And Communications Engineering
Chaitanya Bharati Institute of Technology
08.2012 - 05.2017