HEMANTH KUMAR BALAJI
Summary
Accomplished VLSI Physical Design engineer with extensive experience in delivering 20+ tape-outs across various technology nodes. Expertise in power optimization techniques and collaboration with cross-functional teams to drive project success and enhance design performance.
Overview
14
14
years of professional experience
Work History
Staff Engineer
Samsung Austin Research Company
Austin, USA
04.2022 - Current
- Designed and led fusion-compiler flow focused on GPU power-critical subsystems.
- Implemented In-Design Prime Power (IDPP) flow alongside SNPS for dynamic power optimization.
- Presented at SNUG 2024, showcasing advancements in power management techniques.
- Executed multisource CTS flow setup to perform experimental sweeps, optimizing latency-power balance.
- Engineered leakage optimization recipes, achieving target IDSS specifications.
- Worked with DFT team on successful testing and implementation of LOES feature.
- Collaborated with SNPS team to introduce Prime Closure in signoff process, leading to adoption by Innovus Signoff.
- Enhanced design efficiency through port optimization and component resizing.
Sr Engineer
Qualcomm Technologies Inc.
San Diego, USA
07.2019 - 04.2022
- Successfully taped out five nanometer and four nanometer projects meeting all functional specifications.
- Designed over three million gates, achieving aggressive power performance and area targets.
- Executed custom timing fixes for power domain-oriented designs, optimizing performance and reliability.
- Integrated GPU at top level with custom clock to minimize latency and mitigate aging effects.
- Implemented multi-power domains featuring custom power grid and clock tree with semi-custom routes.
- Collaborated with SoC and RTL teams to optimize GPU interface performance, power, and area.
- Participated in DCD-driven design changes, enhancing project outcomes through proactive collaboration.
- Developed disk and license monitoring analysis tools for enhanced operational oversight.
Physical Design Engineer
GlobalFoundries Inc.
Santa Clara, USA
01.2018 - 07.2019
- Handled 14nm tape-out signoff for two blocks with over 1 million instances at frequencies up to 1 GHz.
- Contributed to design of two hierarchical (NOC) blocks with 750k+ instances at 900 MHz, advancing analysis phase for 7nm project.
- Developed custom clock mesh (spine) architecture, achieving optimal clock latency and power trade-off.
- Created multiple Tcl and Perl scripts to streamline build and signoff flow.
- Attended Innovus Training for both block level and hierarchical design session at Cadence Design systems and got certified.
Staff 1- IC Design Engineer
Broadcom Corporation
Bangalore, India
01.2012 - 12.2015
- Managed multiple blocks through five tapeouts on 32nm, 28nm, 20nm, and 16nm technology nodes, supporting high-speed interconnect product group objectives.
- Engineered high-speed clock solutions from one to two GHz for ASIC SoC and 512 MHz to one GHz for independent PHY products, enhancing product performance.
- Implemented custom H-tree designs on both rectangular and rectilinear blocks to enhance performance.
- Led critical project tapeout and customer meetings during deputation to the US, resulting in promotion recognition.
- Guided junior team members and interns in tools, workflows, and project understanding, fostering skill development and team capability.
Education
M.S - Electrical Engineering
Arizona State University
Tempe, AZ12-2017
B.E - Electrical and Electronics Engineering
Anna University
Chennai, TN, India05-2011
Skills
- VLSI physical design expertise
- Complex block execution
- GPU power optimization
- Dynamic power management
- Timing closure
- Scripting proficiency
- Team mentorship
- EDA Tool expertise: FC, Innovus, Atoptech Aprisa, Formality, PrimeTime, PrimeClosure, Calibre, Conformal LEC, Apache Redhawk, Star RC-XT, infinisim
- Working Knowledge: DSO, Fusion-AI, Cerebrus
Websites
Accomplishments
- Won Industrial Defined Projects Competition - conducted by GE at IIT-Madras, India.
- Worked as Teaching assistant for EE335 and EE352 for four semester from fall 2016 - fall 2017.
- Worked on Clean room as research aid on MOS cap fabrication (HfO2 based MOS capacitor).
- Tau Beta Pi member.
Languages
English
Full Professional
Tamil
Native/ Bilingual
Telugu
Native/ Bilingual
Timeline
Staff Engineer
Samsung Austin Research Company
04.2022 - Current
Sr Engineer
Qualcomm Technologies Inc.
07.2019 - 04.2022
Physical Design Engineer
GlobalFoundries Inc.
01.2018 - 07.2019
Staff 1- IC Design Engineer
Broadcom Corporation
01.2012 - 12.2015
M.S - Electrical Engineering
Arizona State University
B.E - Electrical and Electronics Engineering
Anna University