Himaja Kodati
San Jose,CA
Summary
RFIC Design Engineer with 5+ years of experience delivering high-speed analog and mmWave circuits for coherent optical transceivers (400G–1.6T). Proven expertise across 112–260 GBd optical drivers and TIAs in SiGe BiCMOS, including RF layout, EM modeling, analog circuit design, and tapeout execution. Strong background in signal integrity, bandwidth extension, and system-level performance optimization (SNDR). Experienced in cross-functional collaboration to deliver robust silicon.
Overview
10
10
years of professional experience
Work History
Senior RF Design Engineer - Metro Long Haul Division
MACOM
Milpitas, CA
10.2025 - Current
- Contributed to final design and tapeout of a 112 GBd high-swing (~3 Vppd) optical driver and a 260 GBaud TIA for 1.6T optical systems in SiGe BiCMOS
- Owned RF/mmWave layout and EM verification, ensuring signal integrity and parasitic-aware performance at 100+ GHz
- Designed and implemented analog support circuits, including a peak detector for high-speed signal monitoring
- Ported and integrated mixed-signal support blocks (ADCs, LDOs, bandgaps) across designs
- Performed full-chip EM simulations and post-layout verification, identifying and mitigating bandwidth and stability limitations
Senior RF Design Engineer – Optical Interface Division
Renesas Electronics
San Jose, CA
05.2021 - 10.2025
- Led design and silicon validation of 118 GBd and 128 GBd 4Vppd optical drivers in SiGe BiCMOS for 800ZR and metro long haul optical modules
- Architected and implemented high-linearity driver chains, optimizing bandwidth (>70 GHz), output swing (>2.8 Vpp), and power (< 600mW)
- Designed Tunable peaking networks with 6dB dynamic range, Variable gain amplifiers (VGAs) >12dB dynamic range and programmable bias circuits for PVT robustness
- Performed EM-aware layout and modeling up to 200 GHz, ensuring strong silicon correlation
- Collaborated with DSP vendors to run time domain simulations to optimize driver SNDR
- Led post-silicon bring-up, debug, and characterization
- Automated compliance and datasheet analysis using Python
Analog Design Intern
Texas Instruments
Dallas, TX
06.2020 - 08.2020
- Proposed architecture to mitigate package stress-induced drift in Hall sensors
- Modeled stress effects using silicon data and validated across PVT corners
Mixed-Signal Design Verification & Validation Engineer
Texas Instruments
India
06.2016 - 07.2019
- Led verification and validation of 5 high-precision DAC products
- Developed behavioral models and automated data analysis pipelines
- Executed full-chip validation across SPI, I2C, and PMBus interfaces
Education
Master of Science - Electrical Engineering
Texas A&M University
01-2021
Bachelor of Engineering - Electronics & Communication
BITS Hyderabad
01-2016
Skills
- Tools: Cadence Virtuoso, SpectreRF, EMX, Sonnet, Solido
- Languages: Python, MATLAB, Perl, C, Bash
- HDL: Verilog, Verilog-A, Verilog-AMS, SystemVerilog
CORE EXPERTISE
- Optical Drivers & TIAs (100–260 GBd, 400ZR / 800ZR / 1.6T)
- RFIC / mmWave Circuit Design (up to 200 GHz)
- SiGe BiCMOS Technologies
- Variable gain amplifiers, Peaking techniques
- Signal Integrity, Linearity, Power, Bandwidth optimization
- EM Simulation & Layout (Cadence Virtuoso, EMX, Sonnet)
- Post-Layout Verification & Tapeout Execution
- Yield Analysis & Variation-Aware Design
RESEARCH EXPERIENCE
- Low Phase Noise mmWave VCOs (26–40 GHz, 22nm FDSOI)
- Achieved phase noise down to -113 dBc/Hz with optimized power (17–21 mW)
- Designed high-Q passives and mmWave measurement structures
WORK AUTHORIZATION
H-1B Visa
Timeline
Senior RF Design Engineer - Metro Long Haul Division
MACOM
10.2025 - Current
Senior RF Design Engineer – Optical Interface Division
Renesas Electronics
05.2021 - 10.2025
Analog Design Intern
Texas Instruments
06.2020 - 08.2020
Mixed-Signal Design Verification & Validation Engineer
Texas Instruments
06.2016 - 07.2019
Bachelor of Engineering - Electronics & Communication
BITS Hyderabad
Master of Science - Electrical Engineering
Texas A&M University