Hu Chen

• Developed the NET cut flow for Cadence FastSPICE simulation engine Spectre FX

– cut the netlist by regular nets to further reduce the partition size

– pre-process the partition to improve engine convergence and accuracy

• Developed multiple modules in Synopsys IC Compiler II:
– Pin Assignment (PA): place block pins and top ports based on hierarchical
router results; pre-PA sanity check to detect unfavorable design data or user
constraints; post-PA violation check;
– Top-level Interconnect Planning (TIP): an intuitive tool-set which gives user
the fine control over pin assignment, global routing and repeater insertion;
pre-TIP sanity check; post-TIP violation check;

– Design Hierarchy Management: create/remove physical hierarchies; push-
down/pop-up objects across physical hierarchies;

• Designed a software tool–sta tool to analyze the path sensitization, as executing workloads on a circuit. Implemented in C++. Interfaced sta tool with an architectural-simulator, as well as RTL implementation of CPU pipe-stages, to analyze circuit path sensitization as running real-world applications on CPU.

• Designed the Cache Coherence Module (CCM), as well as the Cache Bus Interface
(CBI) in a dual-core RISC CPU, implementing MESI protocol. A test chip
constructed as the platform for this dual-core CPU, was taped out using UMC’s
55nm process.

• Designed a converter for Ethernet MAC to convert the original Media Indepen-
dent Interface (MII) to Reduced Media Independent Interface (RMII).

• Designed a LCD controller that supports panels of RGB, CPU and LVDS inter-
faces.

• Designed a video-in module which receives video data in BT.601 and BT.656
format and reorganizes the data before storing in memory.
• Designed AHB system for multiple SoC platforms.