Summary
Overview
Work History
Education
Skills
References
Qualifications
Timeline
Generic

HUNG KE VUONG

San Jose,CA

Summary

To obtain a Senior Reliability and Failure Analysis Engineering Manager position that will utilize my 35 plus years technical and human relation skills to best serve the interest of the company.

Overview

35
35
years of professional experience

Work History

Senior Principal Reliability and Failure Analysis Engineer

Rambus Inc
CA
08.2018 - Current
  • Manage 4 Reliability Engineer and 1 Reliability Technician.
  • Plan the overall reliability qualification/ failure analysis schedule and manage the progress.
  • Perform Failure Analysis by using Curve Tracer, C-SAM, SEM, EMMI, X-ray, FIB, … on Integrated Circuit from Internal and External customers.
  • Interface, support and manage multiple top-tier customers such as Samsung, Micron and Skhynix on Quality, Reliability and RMA issues.
  • Interface and manage multiple suppliers such as SCK, ASE and TSMC.
  • Create and execute the Reliability Qualification Plan for Process (8nm, 12 nm 22 nm, 40 nm Process Technology), product and package (FC BGA, BGA, MCM, WLCSP, QFN) qual based on Jedec.
  • Create and execute Board Level reliability Plan.
  • Design High temperature operating Life, HAST and Moisture Resistance board.
  • Perform all ESD, Latch-up, EOS, Surge Test (IEC-61000-4-5) and Live Insertion testing and coordinate with Process, test and design engineer to evaluate and improve ESD, EOS, Latch-up and Surge threshold.

Principal Reliability and Failure Analysis Engineer

Aquantia Inc
CA
01.2016 - 01.2018
  • Manage 2 engineers: 1 Reliability and 1 Quality Engineer.
  • Perform Failure Analysis by using Curve Tracer, C-SAM, SEM, EMMI, X-ray, FIB, on Integrated Circuit from Internal and External customers.
  • Interface, support and manage multiple top-tier customers such as Delphi, Apple, Intel and Cisco on Quality, Reliability and RMA issues.
  • Interface and manage multiple suppliers such as Amkor, SCK, ATK, GF, TSMC.
  • Create and execute the Reliability Qualification Plan for Process (14nm, 28 nm, 40 nm Process Technology), product and package (FC BGA, BGA, MCM, Ball, Cu-pillar) qual based on Jedec and AEC Q100 specification.
  • Create and execute Board Level reliability Plan.
  • Design High temperature operating Life, HAST and Moisture Resistance board.
  • Perform all ESD, Latch-up and Live Insertion testing and coordinate with Process, test and design engineer to evaluate and improve ESD and Latch-up threshold.

Quality/ Reliability and Failure Analysis Engineer

Atmel, Inc
CA
10.2015 - 01.2016
  • Perform Failure Analysis at Component Level from Internal and External customers.
  • Interface, support and manage multiple top-tier customers such as Delphi, Apple.
  • Interface and manage multiple suppliers such as ASE, UMC.
  • Support product line, QA, Reliability, Failure Analysis, Marketing, Sales and Field Application Engineers in responding to customer quality, reliability, RMA related issues and inquiries.
  • Manage and measure customer satisfaction including Customer scorecards, surveys etc.
  • Perform and Execute Board Level Reliability Test.

Supplier/ Customer and Failure Analysis Engineer

Avago Technologies Inc
CA
08.2014 - 07.2015
  • Perform Failure Analysis at Component Level from Internal and External customers.
  • Interface, support and manage multiple top-tier customers such as Cisco, IBM, Google, Oracle, Huawei, ZTE, NetApp, EMC, Ericson, Alcatel…
  • Interface and manage multiple suppliers such as SPIL, ASE, TSMC, Renesas.
  • Design and write HTOL, HTS, PP, MR, TC and preconditioning procedures.
  • Design High temperature operating Life Burn-in Board, burn-in controller and Moisture Resistance board.
  • Qualify new processes (40nm, 90 nm, 0.35, 0.25, 0.18 um)/packages (FlipChip, MCM, aQFN, BGA) technology.
  • Perform all ESD, Latch-up and Live Insertion testing and coordinate with Process, test and design engineer to evaluate and improve ESD and Latch-up threshold.

Principal Reliability and Failure Analysis Engineer

PLX Technology Inc / Avago/ Broadcom
CA
10.2007 - 08.2014
  • Perform Failure Analysis at Board and Component Level from Internal and External customers.
  • Design and write HTOL, HTS, PP, MR, TC and preconditioning procedures.
  • Design High temperature operating Life Burn-in Board, burn-in controller and Moisture Resistance board.
  • Qualify new processes (40nm, 90 nm, 0.35, 0.25, 0.18 um)/packages (FlipChip, MCM, aQFN, BGA) technology.
  • Perform all ESD, Latch-up and Live Insertion testing and coordinate with Process, test and design engineer to evaluate and improve ESD and Latch-up threshold.
  • Perform all Reliability Calculations and issue special reports required by Internal and External customers.
  • Track and maintain lot scheduling information on test in-process.
  • Design and conduct special reliability tests.
  • Assure Supplier Corrective Actions (SCAR) are developed and executed via quality techniques (8-D analysis).
  • Perform supplier selection, evaluation and qualification activities.
  • Perform failure analysis by using Curve tracer, High power microscope, Liquid Crystal analysis, SEM/EDX, Emission Microscopy and micromanipulator.
  • Interface with external and internal customer on technical reliability and Quality issues.

Senior Reliability and Customer Case Complaint Handling Engineer

Advanced Bionics/Boston Scientific, Inc
CA
02.2006 - 01.2007
  • Perform Failure Analysis/ complaint handling/ Write 8D Failure Analysis on Class 3 Implantable Device RMAs (Implantable Medical Devices: Spinal Cord Stimulator (SCS), Cochlear and BION), production and qualification failures down to component level.
  • Perform Failure Analysis/ complaint handling/ write 8D failure analysis report on RMAs IVUS System (Intravascular Ultrasound imaging system).
  • Performed boards Reliability MTBF Prediction on Hybrid.
  • Performed Fault Injections, FMEA, Reliability Block Diagram (RBD), Fault Tree and Event Tree analysis, Maintainability Prediction by using Relex, Risk Management, Plan Do-Check-Act.
  • Performed field return evaluation, disposition, ECO, and Supported on going production include product yield analysis and improvement activities.
  • Perform Failure Analysis and Debug all new ICs with R&D.
  • Performed HALT (Highly Accelerated Life Test) and HASS (Highly Accelerated Screen Stress) on Hybrid, Boards and IVUS System, Implantable devices (Class 3 devices).
  • Experienced in an FDA regulated industry in Medical Device manufacturing.
  • Have a good knowledge in 21 Code of Federal Regulations (CFR), Part 820.

Staff Test Reliability Engineer

Terawave Communication Inc
Hayward, CA
05.2001 - 06.2002
  • Performed boards Reliability MTBF Prediction (for ENET, ATM, DS1, DS3, OC3, OC12 cards..).
  • Performed Fault Injections, FMECA, Reliability Block Diagram (RBD), Fault Tree and Event Tree analysis, Maintainability Prediction by using Relex.
  • Performed HALT (Highly Accelerated Life Test) and HASS (Highly Accelerated Screen Stress) on Component (Pin TIA, 2R Receiver, 155/622 Mhz Optical Module, WDM), Board (ENET, ATM, DS3, DS1, OC3, OC12..) and System (PON) Level.
  • Performed field return evaluation, disposition, ECO, and Supported on going production include product yield analysis and improvement activities.
  • Qualified New Process (0.25 um CMOS), Product and Package (BGA) Technology.
  • Created and executed On Going Reliability (ORT) program.
  • Performed Fan, Passive/Active Components, ASIC and Optical Component qualification.
  • Perform Failure Analysis on all RMAs and internal qualification failures down to component and device levels.

Staff Reliability and Failure Analysis Engineer

3dfx Inc
San Jose, CA
01.1997 - 12.1999
  • Perform Failure Analysis at Board and Component Level from Internal and External customers.
  • Prepare/coordinate all qualification, reliability, special lot acceptance for accelerated stress tests.
  • Design and write HTOL, HTS, PP, MR, TC and preconditioning procedures.
  • Design High temperature operating Life Burn-in Board, burn-in controller and Moisture Resistance board.
  • Qualify new processes (0.35, 0.25, 0.18 um)/packages (TQFP, QFP BGA) technology.
  • Perform all ESD, Latch-up and Live Insertion testing and coordinate with Process, test and design engineer to evaluate and improve ESD and Latch-up threshold.
  • Design and maintain a Reliability DataBase.
  • Perform all Reliability Calculations and issue special reports required by Internal and External customers.
  • Perform reliability evaluation, qualification and monitor (ORT) tests.
  • Track and maintain lot scheduling information on test in-process.
  • Perform failure analysis by using Curve tracer, High power microscope, Liquid Crystal analysis, SEM/EDX, Emission Microscopy (Hypervision and Alpha Innotech) and micromanipulator.
  • Interface with external and internal customer on technical reliability and Quality issues.
  • Research and develop new effective Reliability Testing Methods.
  • Design and conduct System Level Reliability Benchmarking.
  • Evaluate and purchase new equipment's: ESD, HAST, THB, Burn-in Oven.
  • Drive and implement the effective methods to increase test coverage and out-going quality.
  • Develop sampling plan for both processes and assemblies.
  • Develop the process/package qualification, On-going Reliability and Quality method.

Staff Reliability Engineer

S3 Inc
Santa Clara, CA
01.1995 - 01.1997
  • Prepare/coordinate all qualification, reliability, special lot acceptance for accelerated stress tests.
  • Design and write HTOL, HTS, PP, MR, TC and preconditioning procedures.
  • Design High temperature operating Life, burn-in controller and Moisture Resistance board.
  • Write and debug Burn-In program.
  • Qualify new processes/packages technology.
  • Perform all ESD, Latch-up and Live Insertion testing and coordinate with Process, test and design engineer to evaluate and improve ESD and Latch-up threshold.
  • Design and maintain a Reliability DataBase.
  • Perform all Reliability Calculations and issue special reports required by Internal and External customers.
  • Perform reliability evaluation, qualification and monitor (ORT) tests.
  • Track and maintain lot-scheduling information on test in process.
  • Design and conduct special reliability tests.
  • Direct and review failures analyses.
  • Perform failure analysis by using Curve tracer, High power microscope, Liquid Crystal analysis, SEM/EDX.
  • Interface with external and internal customer on technical reliability and Quality issues.
  • Research and develop new effective Reliability Testing Methods.
  • Design and conduct System Level Reliability Benchmarking.

Reliability Engineer

Adaptec
Milpitas, CA
07.1990 - 12.1994
  • Prepare/coordinate all qualification, reliability, special lot acceptance for accelerated stress tests.
  • Design and write HTOL, HTS, PP, MR, TC and preconditioning procedures.
  • Perform device's characterization and design review.
  • Design High temperature operating Life, burn-in controller, HAST and Moisture Resistance board.
  • Write and debug Burn-In program.
  • Perform all ESD, Latch-up and Live Insertion testing and coordinate with Process, test and design engineer to evaluate and improve ESD and Latch-up threshold.
  • Design and maintain a Reliability DataBase.
  • Design and issue Reliability Quarterly Report.
  • Perform all Reliability Calculations and issue special reports required by Internal and External customers.
  • Perform reliability evaluation, qualification and monitor tests.
  • Track and maintain lot scheduling information on test in-process.
  • Design and conduct special reliability tests.
  • Direct and review failures analyses.
  • Perform failure analysis by using Curve tracer, High power microscope, Liquid Crystal analysis, SEM/EDX.
  • Interface with external and internal customer on technical reliability issues.
  • Research and develop new effective Reliability Testing Methods.
  • Evaluate and purchase new equipments.

Education

BSEE - AC/DC Circuit, Digital Design (I &II), Transistor Circuits (I&II), Electromagnetic (I&II), Automatic Control System, Semiconductor Device Physic and Advanced Semiconductor Device Physic, Semiconductor Device Processing, Communication System, Microprocessor System Interface, Package Design and Reliability, Unix, TCP/IP

San Jose State University
San Jose, CA

Mask Layout Certificate - CMOS Circuits and Processes, Lay out I/O Cells, Integrated Analog, Digital and Floor Planning, Perform Physical Verification and Design Rule Checks by using Cadence

ITU University
CA

Internal Mandatory Training - DFMEA, Customer Complaint Handling, FDA Quality System Regulation, 21 Code of Federal Regulations (CFR), Part 820, Risk Assessment and Management

Boston Scientific, Inc
CA

Skills

  • Failure analysis
  • Reliability qualification
  • Process technology
  • Board level testing
  • Customer management
  • Supplier management
  • Quality assurance

References

Available upon request.

Qualifications

Strong knowledge on Military Standard and JEDEC specification., Strong knowledge on AEC Q100, Automotive Standard., Hands-on experience with various testing equipment and techniques., Perform boards Reliability MTBF Prediction, FMECA, Reliability Block Diagram, Fault Tree and Event Tree analysis., Set-up required equipment for HALT, HASS, HASA, DVT.

Timeline

Senior Principal Reliability and Failure Analysis Engineer

Rambus Inc
08.2018 - Current

Principal Reliability and Failure Analysis Engineer

Aquantia Inc
01.2016 - 01.2018

Quality/ Reliability and Failure Analysis Engineer

Atmel, Inc
10.2015 - 01.2016

Supplier/ Customer and Failure Analysis Engineer

Avago Technologies Inc
08.2014 - 07.2015

Principal Reliability and Failure Analysis Engineer

PLX Technology Inc / Avago/ Broadcom
10.2007 - 08.2014

Senior Reliability and Customer Case Complaint Handling Engineer

Advanced Bionics/Boston Scientific, Inc
02.2006 - 01.2007

Staff Test Reliability Engineer

Terawave Communication Inc
05.2001 - 06.2002

Staff Reliability and Failure Analysis Engineer

3dfx Inc
01.1997 - 12.1999

Staff Reliability Engineer

S3 Inc
01.1995 - 01.1997

Reliability Engineer

Adaptec
07.1990 - 12.1994

BSEE - AC/DC Circuit, Digital Design (I &II), Transistor Circuits (I&II), Electromagnetic (I&II), Automatic Control System, Semiconductor Device Physic and Advanced Semiconductor Device Physic, Semiconductor Device Processing, Communication System, Microprocessor System Interface, Package Design and Reliability, Unix, TCP/IP

San Jose State University

Mask Layout Certificate - CMOS Circuits and Processes, Lay out I/O Cells, Integrated Analog, Digital and Floor Planning, Perform Physical Verification and Design Rule Checks by using Cadence

ITU University

Internal Mandatory Training - DFMEA, Customer Complaint Handling, FDA Quality System Regulation, 21 Code of Federal Regulations (CFR), Part 820, Risk Assessment and Management

Boston Scientific, Inc

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