HUY PHAM
McDonough,GA
Summary
ASIC Design Verification with 13 years in SSD, HDD, Automotives projects. Solid familiarity with the steps involved in the creation of an ASIC, including the logic design, verification, RTL coding, synthesis. Team player with strong problem-solving skills to contribute effectively to projects and teams. Steep knowledge in NVMe, PCIe, AMBA protocol, DMAC and simulation tools.
Overview
16
16
years of professional experience
Work History
Principal Design Verification Engineer
Marvell Semiconductor
Santa Clara, CA
07.2020 - Current
- Developed comprehensive test plans based on architecture specification, ensuring thorough coverage of all critical aspects of design functionality.
- Set-up and maintain NVMe IP environment for new project: build new DUT, instantiate new PCIe, bring-up PCIe, NVMe.
- Developing and maintaining performance assessment environments.
- Evaluate NVMe IP performance and collaborate with RTL designer to identify core reasons of poor performance
- Set-up new environment for NVMe IP in which PCIe will be substituted by AXI VIP. This simulation environment is useful for improving simulation time and avoiding PCIe dependence.
- Developing and maintaining UVM environment for HWLL IP: build environment from craft, reuse its models for NVMe IP sub-system and SoC verification
- Build UVM environments for NVMe Wrapper: tested connections between NVMe sub-blocks, NIC400, NI-700, FLR, and HotReset/Warm Reset connections
- Coach, train and give debug suggestion to new engineers. Hold test plan review and give feedback for junior engineers.
- Review and analyze current environments for next project improvement. Conducted toot cause analysis for identified issues.
Staff Design and Verification Engineer
Marvell Semiconductor
Ho Chi Minh City, Viet Nam
05.2014 - 10.2019
- Define topology for MCi matrix and AXI matrix. Define power management plan for MCi subsystem.
- Develop RTL for IP, integrate to chip top, check Lint and CDC, and synthesis. Develop SDC and provide support to PnR and STA team for timing analysis and timing closure.
- Create test plan, developing and maintaining UVM environment from scratch (DMAC, MCI, AXI matrix, SPI).
- Build top chip verification environment for ASIC project (RTL verification/Nelist verification and SDF annotation verification).
- Executed targeted stress tests to validate system performance under extreme conditions, ensuring robustness and stability.
- Implemented coverage-driven verification techniques for improved test effectiveness and resource allocation.
- Work closely with validation team to validate post-silicon of MCi design on board.
Senior Design and Verification Engineer
Renesas Electronics
Ho Chi Minh City, Viet Nam
10.2008 - 05.2014
- Propose solutions and implement to improve performance of L3 cache and IMR’s data cache.
- Work with system architecture to define spec/micro-architecture of DMAC sub-system and RTL development (RTL/Synthesis/LEC/CDC/SDC constraint).
- Defined verification plan for bus matrix, DMAC subsystem, L3 cache.
- Utilizing SystemVerilog, created block level environment for AXI matrix, DMAC subsystem, and L3 cache.
- Verified IPs in charge with SoC environment (ARM CPU/DSM model).
- Generated ATE patterns and debug fail patterns.
- Supported and coached younger engineers on CDC constraints, SDC and verification debug.
- In verification lead job, reviewed verification strategies, test plan and assisted with debugging ATE patterns.
Education
Bachelor of Science - Physics (Telecommunications and Electronics
University of Natural Sciences
Ho Chi Minh City, Viet Nam10.2008
Skills
- SystemVerilog expertise
- SoC Integration
- Verification planning
- Testbench development
- UVM methodology
- Functional Coverage
- Gate-level simulations
- Coverage-driven verification
- Constraint random testing
- RTL design understanding
- IP verification
- Verification tool such as NC sim, VCS and MTI
Timeline
Principal Design Verification Engineer
Marvell Semiconductor
07.2020 - Current
Staff Design and Verification Engineer
Marvell Semiconductor
05.2014 - 10.2019
Senior Design and Verification Engineer
Renesas Electronics
10.2008 - 05.2014
Bachelor of Science - Physics (Telecommunications and Electronics
University of Natural Sciences
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